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1. 发明申请

US20060082415A1 Active load with adjustable common-mode level 失效
公开(公告)号：US20060082415A1
公开(公告)日：2006-04-20
申请号：US11180678
申请日：2005-07-14
申请人： Venugopal Gopinathan , Sherif Galal
发明人： Venugopal Gopinathan , Sherif Galal
IPC分类号： H03F3/45
CPC分类号： H03F3/45659 , H03F2200/513 , H03F2203/45652
摘要： A differential preamplifier includes an active load with adjustable common-mode output level. The active load includes a transistor pair, a resistor pair, and a current source. The transistor load is employed to provide high gain, low offset, and a large bandwidth for the differential preamplifier. The resistor pair and current source are used to increase the common-mode output level of the differential preamplifier and to bias the transistor load. The current source can be varied to provide an adjustable common-mode output level suitable for driving next stage devices. The active load design allows the differential preamplifier to operate using only low power voltage supplies and with small-sized transistors.

2. 发明申请

US20080030273A1 Active load with adjustable common-mode level 有权
标题翻译：主动负载可调共模电平
公开(公告)号：US20080030273A1
公开(公告)日：2008-02-07
申请号：US11905287
申请日：2007-09-28
申请人： Venugopal Gopinathan , Sherif Galal
发明人： Venugopal Gopinathan , Sherif Galal
IPC分类号： H03F3/45
CPC分类号： H03F3/45659 , H03F2200/513 , H03F2203/45652
摘要： A differential preamplifier includes an active load with adjustable common-mode output level. The active load includes a transistor pair, a resistor pair, and a current source. The transistor load is employed to provide high gain, low offset, and a large bandwidth for the differential preamplifier. The resistor pair and current source are used to increase the common-mode output level of the differential preamplifier and to bias the transistor load. The current source can be varied to provide an adjustable common-mode output level suitable for driving next stage devices. The active load design allows the differential preamplifier to operate using only low power voltage supplies and with small-sized transistors.
摘要翻译：差分前置放大器包括具有可调共模输出电平的有源负载。有源负载包括晶体管对，电阻对和电流源。晶体管负载用于为差分前置放大器提供高增益，低偏移和大带宽。电阻对和电流源用于增加差分前置放大器的共模输出电平并偏置晶体管负载。可以改变电流源以提供适于驱动下一级装置的可调共模输出电平。有源负载设计允许差分前置放大器仅使用低功率电源和小尺寸晶体管来工作。

3. 发明申请

US20140062751A1 ASYNCHRONOUS ANALOG-TO-DIGITAL CONVERTER HAVING RATE CONTROL 有权
标题翻译：具有速率控制的异步模数转换器
公开(公告)号：US20140062751A1
公开(公告)日：2014-03-06
申请号：US13599539
申请日：2012-08-30
申请人： Venugopal Gopinathan , Udayan Dasgupta , Ganesan Thiagarajan
发明人： Venugopal Gopinathan , Udayan Dasgupta , Ganesan Thiagarajan
IPC分类号： H03M1/34
CPC分类号： H03M1/12 , H03M1/10 , H03M1/125 , H03M1/126 , H03M1/127 , H03M1/18 , H03M1/181
摘要： An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.
摘要翻译：提供了一种装置。比较电路被配置为接收模拟信号。参考电路耦合到比较电路，并被配置为向比较电路提供多个参考信号。 A转换电路耦合到比较电路，并被配置为检测比较电路的输出的变化。时间数字转换器（TDC）耦合到比较电路。定时器耦合到比较电路。速率控制电路耦合到转换电路。输出电路耦合到速率控制电路和TDC，其中输出电路被配置为输出模拟信号的同步数字表示和模拟信号的异步数字表示中的至少一个。

4. 发明申请

US20130106641A1 CARRIER FREQUENCY OFFSET COMPENSATION IN BEAMFORMING SYSTEMS 有权
标题翻译：波束形成系统中的载波频偏补偿
公开(公告)号：US20130106641A1
公开(公告)日：2013-05-02
申请号：US13284606
申请日：2011-10-28
申请人： Nirmal C. Warke , Srinath Hosur , Venugopal Gopinathan
发明人： Nirmal C. Warke , Srinath Hosur , Venugopal Gopinathan
IPC分类号： H01Q3/00 , G01S13/02
CPC分类号： H04L27/0014 , H04B7/0617 , H04B7/086 , H04L2027/0016 , H04L2027/0018 , H04L2027/0028
摘要： A method for communicating signals in an ultra high bandwidth system that compensates for carrier frequency offset is provided. A baseband transmit signal having a plurality of data bits is generated. The baseband transmit signal is upconverted to a radio frequency (RF) transmit signal using a first local oscillator signal having a first carrier frequency. An offset cancellation for the offset between the first carrier frequency and a second carrier frequency for a second local oscillator signal that is used to downconvert an RF receive signal is calculated. The offset cancellation is applied to a plurality of phase rotators, and the RF transmit signal is transmitted over a phased array.
摘要翻译：提供了一种用于在补偿载波频率偏移的超高带宽系统中传送信号的方法。产生具有多个数据位的基带发送信号。使用具有第一载波频率的第一本机振荡器信号将基带发射信号上变频到射频（RF）发射信号。计算用于下变频RF接收信号的第二本地振荡器信号的第一载波频率和第二载波频率之间的偏移的偏移消除。偏移消除被应用于多个相位旋转器，并且RF发送信号通过相控阵列发送。

5. 发明授权

US08374689B2 Methods and systems for determining vascular bodily lumen information and guiding medical devices 有权
标题翻译：用于确定血管体内信息并指导医疗器械的方法和系统
公开(公告)号：US08374689B2
公开(公告)日：2013-02-12
申请号：US13305610
申请日：2011-11-28
申请人： Venugopal Gopinathan , Raghavan Subramaniyan , Goutam Dutta , Nitin Patil , Abhijit Patki
发明人： Venugopal Gopinathan , Raghavan Subramaniyan , Goutam Dutta , Nitin Patil , Abhijit Patki
IPC分类号： A61B5/00
CPC分类号： A61B5/1075 , A61B5/02007 , A61B5/0538 , A61B5/064 , A61B5/066 , A61B5/068 , A61B5/1076 , A61B5/1079 , A61B5/4851 , A61B5/489 , A61B5/6851 , A61B5/6852 , A61B5/6853 , A61B5/7271 , A61B6/504 , A61B6/5211 , A61B6/541 , A61B8/565 , A61B8/582 , A61B2034/2065 , A61B2090/061 , A61B2090/3966 , A61B2090/3983 , A61B2505/05 , A61B2562/043 , A61B2562/08 , A61M2025/0166 , G06T7/246 , G06T2207/10116 , G06T2207/30021 , G06T2207/30101 , G06T2207/30204 , G06T2207/30241
摘要： Methods and systems for determining information about a vascular bodily lumen are described. An exemplary method includes generating an electrical signal, delivering the electrical signal to a plurality of excitation elements in the vicinity of the vascular bodily lumen, measuring a responsive electrical signal from a plurality of sensing elements in response to the delivered electrical signal, and determining a lumen dimension. Specific embodiments include generating a multiple frequency electrical signal. Another embodiment includes measuring a plurality of responsive signals at a plurality of frequencies. Still other embodiments include using spatial diversity of the excitation elements. Yet other embodiments use method for calibration and de-embedding of such measurements to determine the lumen dimensions. Diagnostic devices incorporating the method are also disclosed, including guide wires, catheters and implants. The methods and systems described herein are advantageous as they do not include injecting a second fluid for the measurements.
摘要翻译：描述了用于确定关于血管体内腔的信息的方法和系统。一种示例性方法包括产生电信号，将电信号传送到血管体腔附近的多个激励元件，响应于输送的电信号测量来自多个感测元件的响应电信号，以及确定流明尺寸。具体实施例包括产生多频电信号。另一实施例包括以多个频率测量多个响应信号。其他实施例包括使用激励元件的空间分集。其他实施例使用用于校准和解嵌这些测量以确定管腔尺寸的方法。还公开了包括引导线，导管和植入物的包括该方法的诊断装置。本文描述的方法和系统是有利的，因为它们不包括为测量注入第二流体。

6. 发明授权

US5498982A High speed comparator with a precise sampling instant 失效
标题翻译：高速比较器具有精确的采样瞬间
公开(公告)号：US5498982A
公开(公告)日：1996-03-12
申请号：US374866
申请日：1995-01-19
申请人： Venugopal Gopinathan , Martin J. Izzard
发明人： Venugopal Gopinathan , Martin J. Izzard
IPC分类号： H03K3/2885 , H03K19/086
CPC分类号： H03K3/2885
摘要： A method and apparatus for reducing aperture uncertainty and kick-back noise in high speed comparators is disclosed. The disclosed method is used in a comparator for comparing a first signal (INP) and a second signal (INM) and having a track mode and a regenerative mode of operation. The steps of this method are as follows. A first input current representing the first signal is switched through a first output node (OUTP) during the track mode and a second input current representing the second signal is switched through a second output node (OUTM) during the track mode. During the regenerative mode, approximately half of the first input current is switched through the first output node (OUTP) and approximately half of the first input current is switched through the second output node (OUTM). Also during the regenerative mode, approximately half of the second input current is switched through the first output node and approximately half of the second input current is switched through the second output node.
摘要翻译：公开了一种用于降低高速比较器中的孔径不确定度和反冲噪声的方法和装置。所公开的方法用于比较第一信号（INP）和第二信号（INM）并具有轨道模式和再生操作模式的比较器。该方法的步骤如下。表示第一信号的第一输入电流在轨道模式期间通过第一输出节点（OUTP）切换，并且在轨道模式期间通过第二输出节点（OUTM）切换表示第二信号的第二输入电流。在再生模式期间，通过第一输出节点（OUTP）切换大约一半的第一输入电流，并且通过第二输出节点（OUTM）切换大约一半的第一输入电流。而且在再生模式期间，第二输入电流的大约一半被切换通过第一输出节点，并且大约一半的第二输入电流被切换通过第二输出节点。

7. 发明授权

US4933644A Common-mode feedback bias generator for operational amplifiers 失效
标题翻译：用于运算放大器的共模反馈偏置发生器
公开(公告)号：US4933644A
公开(公告)日：1990-06-12
申请号：US289351
申请日：1988-12-23
申请人： John W. Fattaruso , Venugopal Gopinathan
发明人： John W. Fattaruso , Venugopal Gopinathan
IPC分类号： H03F3/34 , H03F3/347 , H03F3/45
CPC分类号： H03F3/45659 , H03F2203/45011 , H03F2203/45074 , H03F2203/45188 , H03F2203/45476 , H03F2203/45631 , H03F2203/45641
摘要： A common-mode feedback circuit comprises a reference generator (12) for generating a signal corresponding to a desired common-mode operating point connected to a common-mode bias circuit (14) for generating a second signal corresponding to the common-mode operating point of the outputs (V.sub.out.sup.+, V.sub.out.sup.-) of the fully differential operational amplifier. In the preferred embodiment, the common-mode bias circuit (14) includes a sensing circuit (58) comprising two MOS transistors (60, 62) having sources and drains connected together. The MOS transistors (60, 62) operate in the ohmic region to provide a variable load responsive to the output signals (V.sub.out.sup.+, V.sub.out.sup.-) connected to their gates.
摘要翻译：共模反馈电路包括用于产生对应于连接到共模偏置电路（14）的期望共模工作点的信号的参考发生器（12），用于产生对应于共模工作点的第二信号的全差分运算放大器的输出（Vout +，Vout-）。在优选实施例中，共模偏置电路（14）包括感测电路（58），其包括具有连接在一起的源极和漏极的两个MOS晶体管（60,62）。 MOS晶体管（60,62）在欧姆区域中工作，以响应于连接到它们的栅极的输出信号（Vout +，Vout-）来提供可变负载。

8. 发明授权

US07835387B2 Methods and systems for digitally processing data signals 有权
标题翻译：用于数字处理数据信号的方法和系统
公开(公告)号：US07835387B2
公开(公告)日：2010-11-16
申请号：US12496211
申请日：2009-07-01
申请人： Oscar Agazzi , Venugopal Gopinathan
发明人： Oscar Agazzi , Venugopal Gopinathan
IPC分类号： H04L12/66
CPC分类号： H04B10/6971 , H03M1/0604 , H03M1/0607 , H03M1/0624 , H03M1/0836 , H03M1/1215 , H04B10/6933 , H04B10/697 , H04L7/0062 , H04L25/03057 , H04L25/03159 , H04L2025/03445
摘要： Digital signal processing based methods and systems for receiving electrical and/or optical data signals include electrical receivers, optical receivers, parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a single path receiver. Alternatively, the present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal.
摘要翻译：用于接收电和/或光数据信号的基于数字信号处理的方法和系统包括电接收机，光接收机，并行接收机，多信道接收机，定时恢复方案，并且不限于均衡方案。本发明被实现为单路径接收机。或者，本发明被实现为多路径并行接收机，其中使用以较低速率操作的并行路径来实现模数转换器（“ADC”）和/或数字信号处理器（“DSP”）比接收的数据信号。

9. 发明授权

US07330140B2 Interleaved analog to digital converter with compensation for parameter mismatch among individual converters 有权
标题翻译：交错模数转换器，补偿各转换器之间的参数失配
公开(公告)号：US07330140B2
公开(公告)日：2008-02-12
申请号：US11309081
申请日：2006-06-16
申请人： Jaiganesh Balakrishnan , Venugopal Gopinathan , Sthanunathan Ramakrishnan
发明人： Jaiganesh Balakrishnan , Venugopal Gopinathan , Sthanunathan Ramakrishnan
IPC分类号： H03M1/06
CPC分类号： H03M1/1028 , H03M1/0624 , H03M1/1215
摘要： Interleaved analog to digital converter with compensation for parameter mismatch among individual converters. A reference ADC samples an input signal at substantially the same time instances as an individual converter used in the interleaved ADC. The reference values provided by the reference ADC are compared with the digital codes generated by the converter to generate an error value from which estimates of the gain, DC offset and timing errors are computed using statistical techniques. Timing error thus estimated is used to change the phase of the sampling clock provided to the converter, and the gain and DC offset errors estimated are applied to modify the values of reference voltages applied to the converter, thus compensating for parameter mismatches.
摘要翻译：交错模数转换器，补偿各转换器之间的参数失配。参考ADC在与交错ADC中使用的单独转换器基本相同的时间实例处采样输入信号。由参考ADC提供的参考值与由转换器产生的数字代码进行比较，以产生误差值，利用统计技术来计算增益，直流偏移和定时误差的估计。使用如此估计的定时误差来改变提供给转换器的采样时钟的相位，并且应用估计的增益和DC偏移误差来修改施加到转换器的参考电压的值，从而补偿参数失配。

10. 发明授权

US06927631B2 Wideband CMOS gain stage 失效
标题翻译：宽带CMOS增益级
公开(公告)号：US06927631B2
公开(公告)日：2005-08-09
申请号：US10226228
申请日：2002-08-23
申请人： Sandeep Kumar Gupta , Venugopal Gopinathan
发明人： Sandeep Kumar Gupta , Venugopal Gopinathan
IPC分类号： H03F1/52 , H03F3/45
CPC分类号： H03F1/52 , H03F1/523 , H03F3/45085 , H03F3/45183 , H03F2200/447 , H03F2203/45288 , H03F2203/45292 , H03F2203/45324 , H03F2203/45336 , H03F2203/45398 , H03F2203/45696 , H03F2203/45722
摘要： A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.
摘要翻译： CMOS增益级包括偏置电路，其配置成在没有源极跟随器电路的情况下确保后续级的饱和。 CMOS增益级可选择用于制造CMOS增益级的工艺技术的电源电压大于允许的电源电压。为了保护CMOS增益级中的CMOS器件，公开了可选的漏极到体结结穿通保护电路。各种可选特征可以单独实现和/或以彼此的各种组合来实现。可选功能包括过程电压 - 温度（“PVT”）变化保护电路，其使增益相对独立于过程，电压和/或温度变化。可选功能还包括带宽增强电路。

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