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1. 发明授权

US08101451B1 Method to form a device including an annealed lamina and having amorphous silicon on opposing faces 有权
标题翻译：形成包括退火薄片并在相对面上具有非晶硅的器件的方法
公开(公告)号：US08101451B1
公开(公告)日：2012-01-24
申请号：US12980427
申请日：2010-12-29
申请人： Venkatesan Murali , Christopher J Petti , Theodore Smick , Mohamed M Hilali , Kathy J Jackson , Zhiyong Li , Gopalakrishna Prabhu
发明人： Venkatesan Murali , Christopher J Petti , Theodore Smick , Mohamed M Hilali , Kathy J Jackson , Zhiyong Li , Gopalakrishna Prabhu
IPC分类号： H01L21/00 , H01L31/00
CPC分类号： H01L21/187 , H01L31/072 , H01L31/0747 , H01L31/075 , H01L31/1824 , H01L31/1892 , H01L31/202 , Y02E10/545 , Y02E10/548
摘要： A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to a rigid or semi-rigid pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved. Fabricating the support element in situ may avoid the use of adhesives to attach the lamina to a permanent support element; such adhesives may be unable to tolerate processing temperatures and conditions required to complete the device. In some embodiments, this process flow allows the lamina to be annealed at high temperature, then to have an amorphous silicon layer formed on each face of the lamina following that anneal. A device may be formed which comprises the lamina, such as a photovoltaic cell.
摘要翻译：描述了半导体组件，其中在半导体层的表面上构造支撑元件。形成厚度约为50微米或更小的薄层之后，例如通过镀覆或通过施加前体和原位固化来形成支撑元件，得到支撑元件，其可以用于例如，金属，陶瓷，聚合物等。这与刚性或半刚性的预成形支撑元件形成对比，该刚性或半刚性的预成型支撑元件在其形成之后固定到层板上，或者与施加器晶片相接触，其中层板随后被切割。原位制造支撑元件可以避免使用粘合剂将薄片附着到永久支撑元件上; 这种粘合剂可能不能容忍完成装置所需的加工温度和条件。在一些实施例中，该工艺流程允许薄层在高温下退火，然后在该退火之后具有在层的每个表面上形成的非晶硅层。可以形成包括层的器件，例如光伏电池。

2. 发明授权

US07964431B2 Method to make electrical contact to a bonded face of a photovoltaic cell 有权
标题翻译：与光伏电池的接合面进行电接触的方法
公开(公告)号：US07964431B2
公开(公告)日：2011-06-21
申请号：US12407064
申请日：2009-03-19
申请人： Christopher J Petti , Mohamed M Hilali
发明人： Christopher J Petti , Mohamed M Hilali
IPC分类号： H01L21/00
CPC分类号： H01L31/068 , H01L21/76254 , H01L31/022441 , H01L31/02363 , H01L31/0682 , H01L31/1892 , Y02E10/547
摘要： A photovoltaic cell is formed by bonding a donor body to a receiver element and cleaving a thin lamina from the donor body. Electrical contact is made to the bonded surface of the lamina through vias formed in the lamina. In some embodiments the emitter exists only at the bonded surface or only at the cleaved surface face; the emitter does not wrap through the vias between the surfaces. Wiring contacting each of the two surfaces is formed only at the cleaved face, and one set of wiring contacts the bonded surface through conductive material formed in the vias, insulated from the via sidewalls.
摘要翻译：通过将施主体接合到接收器元件并从施主体切割薄层而形成光伏电池。通过层中形成的通孔对薄片的粘合表面进行电接触。在一些实施方案中，发射体仅存在于接合表面处或仅在切割的表面处存在; 发射器不会穿过表面之间的通孔。仅在断裂面形成接触两个表面中的每一个的布线，并且一组布线通过与通孔侧壁绝缘的通孔中形成的导电材料与接合表面接触。

3. 发明授权

US07422985B2 Method for reducing dielectric overetch using a dielectric etch stop at a planar surface 有权
标题翻译：在平坦表面使用电介质蚀刻停止来减少介电过程的方法
公开(公告)号：US07422985B2
公开(公告)日：2008-09-09
申请号：US11090526
申请日：2005-03-25
申请人： Samuel V Dunton , Christopher J Petti , Usha Raghuram
发明人： Samuel V Dunton , Christopher J Petti , Usha Raghuram
IPC分类号： H01L21/302
CPC分类号： H01L27/1021 , H01L21/76802 , H01L21/76829 , Y10S438/90
摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. In a preferred embodiment, the conductive or semiconductor features are pillars forming vertically oriented diodes. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
摘要翻译：基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。在优选实施例中，导电或半导体特征是形成垂直取向的二极管的柱。不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或半导体功能。

4. 发明授权

US07553611B2 Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure 有权
标题翻译：掩盖重复的覆盖和对准标记，以允许在垂直结构中重复使用光掩模
公开(公告)号：US07553611B2
公开(公告)日：2009-06-30
申请号：US11097496
申请日：2005-03-31
申请人： Yung-Tin Chen , Christopher J Petti , Steven J Radigan , Tanmay Kumar
发明人： Yung-Tin Chen , Christopher J Petti , Steven J Radigan , Tanmay Kumar
IPC分类号： G03C5/00 , G03C1/00
CPC分类号： H01L27/0688 , G03F7/70633 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
摘要： In formation of monolithic three dimensional memory arrays, a photomask may be used more than once. Reuse of a photomask creates second, third or more instances of reference marks used by the stepper to achieve alignment (alignment marks) and to measure alignment achieved (overlay marks) directly above prior instances of the same reference mark. The prior instances of the same reference mark may cause interference with the present instance of the reference mark, complicating alignment and measurement. Using the methods of the present invention, blocking structure is created vertically interposed between subsequent instances of the same reference mark, preventing interference.
摘要翻译：在形成单片三维存储器阵列时，可以使用光掩模多于一次。重新使用光掩模创建步进器使用的第二，第三或更多个参考标记实例，以实现对齐（对齐标记）并且直接在相同参考标记的先前实例之上测量对齐（覆盖标记）。相同参考标记的先前实例可能引起对参考标记的当前实例的干扰，使对准和测量复杂化。使用本发明的方法，垂直插入相同参考标记的后续实例之间的阻挡结构，以防止干扰。

5. 发明授权

US08536448B2 Zener diode within a diode structure providing shunt protection 失效
标题翻译：二极管结构内的齐纳二极管提供分流保护
公开(公告)号：US08536448B2
公开(公告)日：2013-09-17
申请号：US13020849
申请日：2011-02-04
申请人： Christopher J Petti
发明人： Christopher J Petti
IPC分类号： H01L31/00
CPC分类号： H01L27/1421 , H01L31/0747 , H01L31/1892 , Y02E10/50
摘要： A structure to provide a Zener diode to avoid shunt formation is disclosed. An undoped or lightly doped monocrystalline thin semiconductor lamina is cleaved from a donor body which is not permanently affixed to a support element. The lamina may be annealed at high temperature to remove damage from a prior implant. At least one aperture is formed through the lamina, either due to flaws in the cleaving process, or intentionally following cleaving. Heavily doped amorphous silicon layers having opposite conductivity types are deposited on opposite faces of the lamina, one forming the emitter and one a base contact to a photovoltaic cell, while the lamina forms the base of the cell. The heavily doped layers contact in the aperture, forming a Zener diode. This Zener diode prevents formation of shunts, and may behave as a bypass diode if the cell is placed under heavy reverse bias, as when one cell in a series string is shaded while the rest of the string is exposed to sun.
摘要翻译：公开了提供齐纳二极管以避免分流形成的结构。未掺杂或轻掺杂的单晶薄半导体层从不永久地固定到支撑元件的施主体断开。层可以在高温下退火以去除以前的植入物的损伤。由于切割过程中的缺陷，或者故意在切割之后，至少一个孔通过层形成。具有相反导电类型的重掺杂非晶硅层沉积在层的相对表面上，一个形成发射极，另一个与光伏电池的基极接触，而薄层形成电池的基极。重掺杂层在孔中接触，形成齐纳二极管。该齐纳二极管防止分流器的形成，并且如果电池放置在较强的反向偏压下，则可能表现为旁路二极管，如串联串中的一个电池阴影而串的其余部分暴露在阳光下时。

6. 发明授权

US08004013B2 Polycrystalline thin film bipolar transistors 有权
标题翻译：多晶薄膜双极晶体管
公开(公告)号：US08004013B2
公开(公告)日：2011-08-23
申请号：US11763816
申请日：2007-06-15
申请人： Christopher J Petti , S. Brad Herner
发明人： Christopher J Petti , S. Brad Herner
IPC分类号： H01L31/0336 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/7317 , G11C5/025 , G11C11/416 , H01L27/0688 , H01L27/1022 , H01L29/456 , H01L29/735
摘要： A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide is described. The emitter region and collector region also may comprise polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide.
摘要翻译：一种半导体器件，包括具有基极区域，发射极区域和集电极区域的双极晶体管，其中所述基极区域包括通过使与硅化物，锗化物或硅化物锗化物接触的硅，锗或锗锗结晶而形成的多晶半导体材料。发射极区域和集电极区域还可以包括通过使硅，锗或锗锗与硅化物，锗化锗或锗化锗形成金属接触而形成的多晶半导体材料。多晶半导体材料优选为与C49相钛硅化物接触形成的硅化多晶硅。

7. 发明授权

US08748859B2 Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars 有权
标题翻译：非易失性存储器阵列包括具有用于电隔离柱的二极管的共享二极管组件部分的轨道堆叠
公开(公告)号：US08748859B2
公开(公告)日：2014-06-10
申请号：US13441805
申请日：2012-04-06
申请人： Kang-Jay Hsia , Christopher J Petti , Calvin K Li
发明人： Kang-Jay Hsia , Christopher J Petti , Calvin K Li
IPC分类号： H01L29/02
CPC分类号： H01L27/1021
摘要： An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.
摘要翻译：提供了一种在导体之间包括垂直取向的二极管结构的集成电路及其制造方法。诸如无源元件存储单元的两端器件可以包括与反熔丝和/或其他状态改变元件串联的二极管操作元件。这些装置在上下导体组的交点处使用支柱结构形成。通过在轨道堆叠中的每个支柱的一个导体上形成二极管的一部分来减小柱结构的高度。一个实施例中的二极管可以包括第一导电类型的第一二极管部件和第二导电类型的第二二极管部件。二极管部件之一的一部分被分成第一和第二部分，其中一部分形成在轨道堆叠中，其中与在轨道堆叠处使用柱形成的其他二极管共用。

8. 发明授权

US08410353B2 Asymmetric surface texturing for use in a photovoltaic cell and method of making 失效
标题翻译：用于光伏电池的非对称表面纹理及其制造方法
公开(公告)号：US08410353B2
公开(公告)日：2013-04-02
申请号：US13048955
申请日：2011-03-16
申请人： Christopher J Petti
发明人： Christopher J Petti
IPC分类号： H02N3/00 , H01L31/042 , H01L31/00
CPC分类号： H01L31/02363 , H01L31/02167 , H01L31/02168 , Y02E10/50
摘要： A novel surface texturing provides improved light-trapping characteristics for photovoltaic cells. The surface is asymmetric and includes shallow slopes at between about 5 and about 30 degrees from horizontal as well as steeper slopes at about 70 degrees or more from horizontal. It is advantageously used as either the front or back surface of a thin semiconductor lamina, for example between about 1 and about 20 microns thick, which comprises at least the base or emitter of a photovoltaic cell. In embodiments of the present invention, the shallow slopes are formed using imprint photolithography.
摘要翻译：新颖的表面纹理为光伏电池提供了改进的光捕获特性。表面是不对称的，并且包括与水平方向在大约5度和大约30度之间的浅斜面以及从水平方向大约70度或更大的更陡峭的斜面。它有利地用作薄半导体层的前表面或后表面，例如约1至约20微米厚，其至少包括光伏电池的基极或发射极。在本发明的实施例中，使用压印光刻形成浅斜面。

9. 发明授权

US07927990B2 Forming complimentary metal features using conformal insulator layer 有权
标题翻译：使用保形绝缘层形成互补的金属特征
公开(公告)号：US07927990B2
公开(公告)日：2011-04-19
申请号：US11771137
申请日：2007-06-29
申请人： Kang-Jay Hsia , Calvin K Li , Christopher J Petti
发明人： Kang-Jay Hsia , Calvin K Li , Christopher J Petti
IPC分类号： H01L21/20
CPC分类号： H01L21/76838 , H01L21/76834 , H01L27/1021
摘要： A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the first metal lines. The second metal layer is planarized to form second metal lines interposed between the first metal lines, coexposing the thin dielectric layer and the second metal layer at a substantially planar surface. In some embodiments, planarization continues to remove the thin dielectric covering tops of the first metal lines, coexposing the first metal lines and the second metal lines, separated by the thin dielectric layer, at a substantially planar surface.
摘要翻译：提供了一种形成密集间隔的金属线的方法。通过蚀刻第一金属层形成第一组金属线。平坦地沉积在第一金属线上的薄介电层。第二金属沉积在薄介电层上，填充第一金属线之间的间隙。第二金属层被平坦化以形成插入在第一金属线之间的第二金属线，在基本上平坦的表面处共存薄介电层和第二金属层。在一些实施例中，平面化继续移除第一金属线的薄电介质覆盖顶部，在基本上平坦的表面处将第一金属线和由薄介电层隔开的第二金属线并入。

10. 发明授权

US07800933B2 Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance 有权
标题翻译：一种用于使用具有可调整电阻的可切换半导体存储元件的存储单元的方法
公开(公告)号：US07800933B2
公开(公告)日：2010-09-21
申请号：US11496986
申请日：2006-07-31
申请人： Tanmay Kumar , S. Brad Herner , Roy E Scheuerlein , Christopher J Petti
发明人： Tanmay Kumar , S. Brad Herner , Roy E Scheuerlein , Christopher J Petti
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C11/5692 , G11C13/0069 , G11C17/14 , G11C17/165 , G11C2013/0073 , H01L27/101
摘要： A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias, while reset pulses are applied with the diode in reverse bias. By switching resistivity of the semiconductor material of the diode, a memory cell can be either one-time programmable or rewriteable, and can achieve two, three, four, or more distinct data states.
摘要翻译：包括由半导体材料形成的二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变半导体材料的电阻来存储存储器状态。在优选实施例中，施加设定脉冲二极管在正向偏置下，而复位脉冲以二极管反向施加。通过切换二极管的半导体材料的电阻率，存储器单元可以是一次性可编程的或可重写的，并且可以实现两个，三个，四个或更多个不同的数据状态。

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