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1. 发明授权

US08629526B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08629526B2
公开(公告)日：2014-01-14
申请号：US13233941
申请日：2011-09-15
申请人： Tsuyoshi Ohta , Masatoshi Arai , Miwako Suzuki
发明人： Tsuyoshi Ohta , Masatoshi Arai , Miwako Suzuki
IPC分类号： H01L29/47
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/36 , H01L29/402 , H01L29/66136 , H01L29/66143 , H01L29/861
摘要： According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type and a first electrode. The second regions are provided separately on a first major surface side of the first layer. The third region is provided on the first major surface side of the first layer so as to surround the second regions. The first electrode is provided on the first layer and the second regions. The first layer has a first portion and a second portion. The second portion has a lower resistivity than the first portion. The second portion is provided between the second regions and between the first portion and the first major surface and is provided outside the third region and between the first portion and the first major surface.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的第一半导体层，第二导电类型的多个第二半导体区域，第二导电类型的第三半导体区域和第一电极。第二区域分别设置在第一层的第一主表面侧。第三区域设置在第一层的第一主表面侧，以围绕第二区域。第一电极设置在第一层和第二区域上。第一层具有第一部分和第二部分。第二部分具有比第一部分更低的电阻率。第二部分设置在第二区域之间以及第一部分与第一主表面之间，并且设置在第三区域的外部以及第一部分与第一主表面之间。

2. 发明授权

US08723253B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08723253B2
公开(公告)日：2014-05-13
申请号：US13239101
申请日：2011-09-21
申请人： Tsuyoshi Ohta , Masatoshi Arai , Miwako Suzuki
发明人： Tsuyoshi Ohta , Masatoshi Arai , Miwako Suzuki
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0856 , H01L29/0865 , H01L29/1095 , H01L29/167 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/7397 , H01L29/861 , H01L29/8725
摘要： According to one embodiment, the semiconductor device includes a first semiconductor layer. The semiconductor device includes a plurality of base regions, the base regions are provided on a surface of the first semiconductor layer. The semiconductor device includes a source region selectively provided on each of surfaces of the base regions. The semiconductor device includes a gate electrode provided via a gate insulating film in each of a pair of trenches, each of the trenches penetrate the base regions from a surface of the source region to the first semiconductor layer. The semiconductor device includes a field plate electrode provided via a field plate insulating film in each of the pair of trenches under the gate electrode. A thickness of a part of the field plate insulating film is greater than a thickness of the gate insulating film.
摘要翻译：根据一个实施例，半导体器件包括第一半导体层。所述半导体器件包括多个基极区域，所述基极区域设置在所述第一半导体层的表面上。半导体器件包括选择性地设置在基极区域的每个表面上的源极区域。半导体器件包括在一对沟槽中的每一个中经由栅极绝缘膜提供的栅电极，每个沟槽从源极区域的表面到第一半导体层穿透基极区域。半导体器件包括在栅电极下的一对沟槽中的每一个中经由场板绝缘膜设置的场板电极。场板绝缘膜的一部分的厚度大于栅极绝缘膜的厚度。

3. 发明授权

US08552476B2 Schottky barrier diode and MOSFET semiconductor device 有权
标题翻译：肖特基势垒二极管和MOSFET半导体器件
公开(公告)号：US08552476B2
公开(公告)日：2013-10-08
申请号：US13236588
申请日：2011-09-19
申请人： Tsuyoshi Ohta , Masatoshi Arai , Miwako Suzuki
发明人： Tsuyoshi Ohta , Masatoshi Arai , Miwako Suzuki
IPC分类号： H01L29/80 , H01L29/66 , H01L29/76 , H01L29/47
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/407 , H01L29/42368 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/7806 , H01L29/872 , H01L29/8725
摘要： A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.
摘要翻译：半导体层具有第二杂质浓度。第一沟槽形成在半导体层中，从半导体层的上表面向下延伸。每个绝缘层沿着第一沟槽的每个内壁形成。每个导电层被形成为经由每个绝缘层埋入每个第一沟槽，并且从半导体层的上表面向下延伸到第一位置。第一半导体扩散层从半导体层的上表面到达第二位置，位于第一沟槽之间，并且具有低于第二杂质浓度的第三杂质浓度。从半导体层的上表面到第二位置的长度等于或小于从半导体层的上表面到第一位置的一半长度。

4. 发明申请

US20120241898A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120241898A1
公开(公告)日：2012-09-27
申请号：US13419395
申请日：2012-03-13
申请人： Tsuyoshi Ohta , Masatoshi Arai , Miwako Suzuki , Tadashi Matsuda
发明人： Tsuyoshi Ohta , Masatoshi Arai , Miwako Suzuki , Tadashi Matsuda
IPC分类号： H01L29/47
CPC分类号： H01L29/66136 , H01L29/0623 , H01L29/0692 , H01L29/66143 , H01L29/861 , H01L29/868 , H01L29/872 , H01L29/8725
摘要： According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second semiconductor region of the first conductivity type and a second electrode. The first semiconductor region includes a first portion including a first major surface and a second portion extending in a first direction perpendicular to the first major surface on the first major surface. The first electrode includes a third portion provided to face the second portion and is provided to be separated from the first semiconductor region. The second semiconductor region is provided between the second and third portions, includes a first concentration region having a lower impurity concentration than the first semiconductor region and forms a Schottky junction with the third portion. The second electrode is provided on an opposite side of the first major surface and in conduction with the first portion.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的第一半导体区域，第一电极，第一导电类型的第二半导体区域和第二电极。第一半导体区域包括包括第一主表面的第一部分和在垂直于第一主表面上的第一主表面的第一方向上延伸的第二部分。第一电极包括设置成面对第二部分的第三部分，并且设置成与第一半导体区域分离。第二半导体区域设置在第二和第三部分之间，包括具有比第一半导体区域低的杂质浓度的第一浓度区域，并与第三部分形成肖特基结。第二电极设置在第一主表面的相反侧并与第一部分导通。

5. 发明授权

US08502305B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08502305B2
公开(公告)日：2013-08-06
申请号：US13421816
申请日：2012-03-15
申请人： Tsuyoshi Ohta , Tatsuya Nishiwaki , Norio Yasuhara , Masatoshi Arai , Takahiro Kawano
发明人： Tsuyoshi Ohta , Tatsuya Nishiwaki , Norio Yasuhara , Masatoshi Arai , Takahiro Kawano
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L21/2255 , H01L21/26586 , H01L29/0696 , H01L29/0856 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/861
摘要： According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region.
摘要翻译：根据实施例，半导体器件包括第一导电类型的半导体层，设置在半导体层上的第二导电类型的基极区域和设置在基极区域上的第二导电类型的第一接触区域。该器件包括设置在穿过第一接触区域和基极区域的沟槽中的栅电极，以及设置在栅极上并包含第一导电型杂质元素的层间绝缘膜。该器件还包括设置在层间绝缘膜和第一接触区域之间的第一导电类型的源极区域，源极区域与层间绝缘膜的侧面接触并且在基极区域中延伸。

6. 发明授权

US09153608B2 Photodiode array, method for determining reference voltage, and method for determining recommended operating voltage 有权
标题翻译：光电二极管阵列，确定参考电压的方法以及确定推荐工作电压的方法
公开(公告)号：US09153608B2
公开(公告)日：2015-10-06
申请号：US13247192
申请日：2011-09-28
申请人： Kenichi Sato , Shogo Kamakura , Shigeyuki Nakamura , Tsuyoshi Ohta , Michito Hirayanagi , Hiroki Suzuki , Shunsuke Adachi
发明人： Kenichi Sato , Shogo Kamakura , Shigeyuki Nakamura , Tsuyoshi Ohta , Michito Hirayanagi , Hiroki Suzuki , Shunsuke Adachi
IPC分类号： H01J40/14 , H01F3/08 , H03K17/78 , H01L27/00 , H01J31/50 , H01L27/144
CPC分类号： H01L27/1446
摘要： A reverse bias voltage is applied to a photodiode array provided with a plurality of avalanche photodiodes operated in Geiger mode and with quenching resistors connected in series to the respective avalanche photodiodes. Electric current is measured with change of the reverse bias voltage applied, and the reverse bias voltage at an inflection point in change of electric current measured is determined as a reference voltage. A voltage obtained by adding a predetermined value to the determined reference voltage is determined as a recommended operating voltage.
摘要翻译：反向偏置电压被施加到设置有以盖革模式操作的多个雪崩光电二极管的光电二极管阵列，以及与相应的雪崩光电二极管串联连接的淬火电阻器。以施加的反向偏置电压的变化来测量电流，并且将测量的电流变化中的拐点处的反向偏置电压确定为参考电压。将通过将预定值加到所确定的参考电压而获得的电压被确定为推荐的工作电压。

7. 发明申请

US20070145416A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20070145416A1
公开(公告)日：2007-06-28
申请号：US11616603
申请日：2006-12-27
申请人： Tsuyoshi Ohta , Bungo Tanaka
发明人： Tsuyoshi Ohta , Bungo Tanaka
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0649 , H01L29/0696 , H01L29/4236 , H01L29/42372 , H01L29/4925 , H01L29/4958 , H01L29/7397
摘要： A semiconductor device comprises on a surface of a first semiconductor layer of the first conduction type a second semiconductor layer of the first conduction type. A semiconductor base layer of the second conduction type is formed on the second semiconductor layer, and a semiconductor diffusion layer of the first conduction type is formed on a surface of the semiconductor base layer. A trench is formed from the surface of the semiconductor diffusion layer to a depth reaching the second semiconductor layer. A gate electrode is formed of a conductor film buried in the trench with a gate insulator interposed therebetween. The conductor film includes a first conductor film formed along the gate electrode to have a recess and a second conductor film formed to fill the recess.
摘要翻译：半导体器件包括在第一导电类型的第一半导体层的表面上的第一导电类型的第二半导体层。第二导电类型的半导体基层形成在第二半导体层上，并且在半导体基底层的表面上形成第一导电类型的半导体扩散层。从半导体扩散层的表面到到达第二半导体层的深度形成沟槽。栅电极由埋在沟槽中的导体膜形成，栅极绝缘体插入其间。导体膜包括沿着栅电极形成以具有凹部的第一导体膜和形成为填充凹部的第二导体膜。

8. 发明授权

US5556729A Negatively chargeable electrophotographic photoreceptor 失效
标题翻译：可负电荷的电子照相感光体
公开(公告)号：US5556729A
公开(公告)日：1996-09-17
申请号：US464466
申请日：1995-06-05
申请人： Yuzuru Fukuda , Tsuyoshi Ohta , Masato Ono , Taketoshi Higashi , Shigeru Yagi
发明人： Yuzuru Fukuda , Tsuyoshi Ohta , Masato Ono , Taketoshi Higashi , Shigeru Yagi
IPC分类号： G03G5/08 , G03G5/082 , G03G5/147
CPC分类号： G03G5/08235 , G03G5/08278
摘要： An electrophotographic photoreceptor comprising: an electrically conductive substrate, a charge injection blocking layer formed on said electrically conductive substrate, a photoconductive layer comprising a single layer formed on said charge injection blocking layer, said photoconductive layer comprising amorphous silicon containing boron, a positive hole capturing layer formed on said photoconductive layer, said positive hole capturing layer being selected from the group comprising amorphous silicon containing less than 50 ppm boron and amorphous silicon being substantially composed of hydrogen and silicon atoms, and a surface layer formed on said positive hole capturing layer. The boron concentration contained in said photoconductive layer is 0.01-1000 ppm. The surface layer is formed by amorphous silicon nitride, amorphous silicon oxide, amorphous silicon carbide or amorphous carbon as a main body. The charge injection blocking layer has amorphous silicon as a main body and contains a group V element. The electrophotographic photoreceptor is excellent in the dark attenuation, the sensitivity and electrification capacity and does not cause image flow or image fogging on copied images obtained by using the photoreceptor.
摘要翻译：一种电子照相感光体，其特征在于，具有：导电性基板，形成在所述导电性基板上的电荷注入阻挡层，含有形成于所述电荷注入阻挡层上的单层的光电导层，所述光电导层含有含硼的非晶硅，所述空穴捕获层选自含有小于50ppm硼的非晶硅和基本上由氢和硅原子组成的非晶硅，以及形成在所述正空穴捕获层上的表面层。所述光电导层中含有的硼浓度为0.01〜1000ppm。表面层由非晶氮化硅，非晶氧化硅，非晶碳化硅或无定形碳作为主体形成。电荷注入阻挡层以非晶硅为主体，含有V族元素。电子照相感光体在黑暗衰减，灵敏度和带电能力方面优异，并且不会对通过使用感光体获得的复印图像上的图像流动或图像起雾。

9. 外观设计

USD589698S1 Key case 有权
公开(公告)号：USD589698S1
公开(公告)日：2009-04-07
申请号：US29323741
申请日：2008-08-29
申请人： Tsuyoshi Ohta , Rumi Ohta
设计人： Tsuyoshi Ohta , Rumi Ohta

10. 发明授权

US5721526A Compact high-voltage variable resistor 失效
标题翻译：紧凑型高压可变电阻
公开(公告)号：US5721526A
公开(公告)日：1998-02-24
申请号：US683706
申请日：1996-07-18
申请人： Kazufumi Daimon , Tsuyoshi Ohta , Kenichi Hiraki
发明人： Kazufumi Daimon , Tsuyoshi Ohta , Kenichi Hiraki
IPC分类号： H01C10/32 , H01C10/30
CPC分类号： H01C10/32
摘要： A high-voltage variable resistor capable of significantly reducing a circuit board as compared with a prior art. Terminal fitments each are arranged so as to function as a connector for forming electrical connection between a slide element slid on each of variable resistance patterns and a terminal acting as an output section. A contact point between a contact on a contact support of the terminal fitment and a plate-like member of the slide element is positioned apart from a surface of the circuit board. The terminal fitment includes a positioner, which is positioned outside the pattern in a radial direction thereof, so that the positioner intersects the pattern while being spaced therefrom.
摘要翻译：与现有技术相比，能够显着地减少电路板的高压可变电阻器。端子配件各自布置成用作用于在滑动每个可变电阻图案的滑动元件和用作输出部分的端子之间形成电连接的连接器。端子配件的触点支撑件上的触点与滑动元件的板状元件之间的接触点位于与电路板的表面分开的位置。端子配件包括定位器，其定位在图案的径向方向外侧，使得定位器与图案间隔开。

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