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1. 发明授权

US07977800B2 Semiconductor device and fabrication method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07977800B2
公开(公告)日：2011-07-12
申请号：US12247518
申请日：2008-10-08
申请人： Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
发明人： Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
IPC分类号： H01L21/8234
CPC分类号： H01L23/535 , H01L21/28518 , H01L21/28525 , H01L21/76895 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L27/11 , H01L29/161 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
摘要翻译：半导体器件包括：晶体管，其具有形成在半导体衬底上的栅极电极和形成在半导体衬底的位于栅电极两侧的部分中的第一和第二源极/漏极区域; 形成在相对于第一源极/漏极区域的与栅电极相对的位置处的栅极互连; 以及形成在所述第一源极/漏极区域上以在所述半导体衬底的顶表面上方突出的第一硅 - 锗层。栅极互连和第一源极/漏极区域经由包括第一硅 - 锗层的局部互连结构连接。

2. 发明申请

US20110227168A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110227168A1
公开(公告)日：2011-09-22
申请号：US13149554
申请日：2011-05-31
申请人： Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
发明人： Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
IPC分类号： H01L29/78
CPC分类号： H01L23/535 , H01L21/28518 , H01L21/28525 , H01L21/76895 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L27/11 , H01L29/161 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
摘要翻译：半导体器件包括：晶体管，其具有形成在半导体衬底上的栅极电极和形成在半导体衬底的位于栅电极两侧的部分中的第一和第二源极/漏极区域; 形成在相对于第一源极/漏极区域的与栅电极相对的位置处的栅极互连; 以及形成在所述第一源极/漏极区域上以在所述半导体衬底的顶表面上方突出的第一硅 - 锗层。栅极互连和第一源极/漏极区域经由包括第一硅 - 锗层的局部互连结构连接。

3. 发明授权

US08350332B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08350332B2
公开(公告)日：2013-01-08
申请号：US12619222
申请日：2009-11-16
申请人： Tsutomu Oosuka , Yoshihiro Sato , Hisashi Ogawa
发明人： Tsutomu Oosuka , Yoshihiro Sato , Hisashi Ogawa
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/823462 , H01L21/823481 , H01L21/823857 , H01L21/823878
摘要： A first and second gate electrodes are formed on a first and second active regions, respectively. The first and second gate electrodes have a first and second metal-containing conductive films, respectively. The first and second metal-containing conductive films are formed on the isolation region for segmenting the first and second active regions to be spaced apart from each other. A third metal-containing conductive film, which is a part of each of the first and second gate electrodes, is continuously formed from a top of the first metal-containing conductive film through a top of the isolation region to a top of the second metal-containing conductive film. The third metal-containing conductive film is in contact with the first and second metal-containing conductive films.
摘要翻译：第一和第二栅电极分别形成在第一和第二有源区上。第一和第二栅电极分别具有第一和第二含金属的导电膜。第一和第二含金属导电膜形成在隔离区域上，用于将第一和第二有源区域彼此分隔开。作为第一和第二栅电极中的每一个的一部分的第三含金属导电膜从第一含金属导电膜的顶部通过隔离区的顶部连续地形成到第二金属的顶部的导电膜。第三含金属导电膜与第一和第二含金属导电膜接触。

4. 发明授权

US08344455B2 Semiconductor device and fabrication method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08344455B2
公开(公告)日：2013-01-01
申请号：US13149554
申请日：2011-05-31
申请人： Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
发明人： Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
IPC分类号： H01L29/78
CPC分类号： H01L23/535 , H01L21/28518 , H01L21/28525 , H01L21/76895 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L27/11 , H01L29/161 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
摘要翻译：半导体器件包括：晶体管，其具有形成在半导体衬底上的栅极电极和形成在半导体衬底的位于栅电极两侧的部分中的第一和第二源极/漏极区域; 形成在相对于第一源极/漏极区域的与栅电极相对的位置处的栅极互连; 以及形成在所述第一源极/漏极区域上以在所述半导体衬底的顶表面上方突出的第一硅 - 锗层。栅极互连和第一源极/漏极区域经由包括第一硅 - 锗层的局部互连结构连接。

5. 发明申请

US20110169100A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110169100A1
公开(公告)日：2011-07-14
申请号：US13005085
申请日：2011-01-12
申请人： Hiroji SHIMIZU , Yoshihiro Sato , Hideyuki Arai , Takayuki Yamada , Tsutomu Oosuka
发明人： Hiroji SHIMIZU , Yoshihiro Sato , Hideyuki Arai , Takayuki Yamada , Tsutomu Oosuka
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L27/0629 , H01L28/20
摘要： A semiconductor device includes: a first MIS transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of silicon formed on the second high dielectric film. The first high dielectric film and the second high dielectric film include the same high dielectric material, and the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal.
摘要翻译：一种半导体器件包括：第一导电类型的第一MIS晶体管，具有作为由半导体衬底的上部形成的元件隔离区围绕的半导体衬底的区域的第一有源区，第一栅绝缘膜，形成在第一有源区上的高电介质膜和形成在第一栅极绝缘膜上的第一栅电极; 以及电阻元件，其具有形成在元件隔离区域上的第二高电介质膜和形成在第二高介电膜上的由硅制成的电阻层。第一高介电膜和第二高电介质膜包括相同的高介电材料，第一高电介质膜包括第一调节金属，但第二高电介质膜不包括第一调节金属。

6. 发明授权

US08558321B2 Semiconductor device having gate insulating film including high dielectric material 有权
标题翻译：具有包括高电介质材料的栅极绝缘膜的半导体器件
公开(公告)号：US08558321B2
公开(公告)日：2013-10-15
申请号：US13005085
申请日：2011-01-12
申请人： Hiroji Shimizu , Yoshihiro Sato , Hideyuki Arai , Takayuki Yamada , Tsutomu Oosuka
发明人： Hiroji Shimizu , Yoshihiro Sato , Hideyuki Arai , Takayuki Yamada , Tsutomu Oosuka
IPC分类号： H01L21/40
CPC分类号： H01L27/0629 , H01L28/20
摘要： A semiconductor device includes: a first MIS transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of silicon formed on the second high dielectric film. The first high dielectric film and the second high dielectric film include the same high dielectric material, and the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal.
摘要翻译：一种半导体器件包括：第一导电类型的第一MIS晶体管，具有作为由半导体衬底的上部形成的元件隔离区围绕的半导体衬底的区域的第一有源区，第一栅绝缘膜，形成在第一有源区上的高电介质膜和形成在第一栅极绝缘膜上的第一栅电极; 以及电阻元件，其具有形成在元件隔离区域上的第二高电介质膜和形成在第二高介电膜上的由硅制成的电阻层。第一高介电膜和第二高电介质膜包括相同的高介电材料，第一高电介质膜包括第一调节金属，但第二高电介质膜不包括第一调节金属。

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