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1. 发明授权

US09117831B2 Seal ring structure for integrated circuit chips 有权
标题翻译：集成电路芯片的密封环结构
公开(公告)号：US09117831B2
公开(公告)日：2015-08-25
申请号：US13004261
申请日：2011-01-11
申请人： Ching-Jung Yang , Yu-Wen Liu , Michael Shou-Ming Tong , Hsien-Wei Chen , Chung-Ying Yang , Tsung-Yuan Yu
发明人： Ching-Jung Yang , Yu-Wen Liu , Michael Shou-Ming Tong , Hsien-Wei Chen , Chung-Ying Yang , Tsung-Yuan Yu
IPC分类号： H01L23/00 , H01L23/58
CPC分类号： H01L23/564 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate having a circuit region and a seal ring region. The seal ring region surrounds the circuit region. A seal ring structure is disposed over the seal ring region. The seal ring structure has a first portion and a second portion above the first portion. The first portion has a width W1, and the second portion has a width W2. The width W1 is less than the width W2.
摘要翻译：半导体器件包括具有电路区域和密封环区域的衬底。密封圈区域围绕电路区域。密封环结构设置在密封环区域的上方。密封环结构具有在第一部分上方的第一部分和第二部分。第一部分具有宽度W1，第二部分具有宽度W2。宽度W1小于宽度W2。

2. 发明授权

US08624359B2 Wafer level chip scale package and method of manufacturing the same 有权
标题翻译：晶圆级芯片尺寸封装及其制造方法
公开(公告)号：US08624359B2
公开(公告)日：2014-01-07
申请号：US13253845
申请日：2011-10-05
申请人： Chung-Ying Yang , Hsien-Wei Chen , Tsung-Yuan Yu , Shih-Wei Liang
发明人： Chung-Ying Yang , Hsien-Wei Chen , Tsung-Yuan Yu , Shih-Wei Liang
IPC分类号： H01L23/544
CPC分类号： H01L23/3142 , H01L21/561 , H01L21/563 , H01L21/568 , H01L21/76895 , H01L23/3114 , H01L23/5226 , H01L23/528 , H01L23/562 , H01L23/564 , H01L23/585 , H01L24/05 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/96 , H01L2224/02377 , H01L2224/0401 , H01L2224/04105 , H01L2224/05569 , H01L2224/05572 , H01L2224/12105 , H01L2224/131 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2224/05552
摘要： A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.
摘要翻译：晶片级芯片级封装（WLCSP）包括具有接触焊盘的有源表面和侧表面的半导体器件。模具覆盖半导体器件的侧表面。 RDL结构包括电连接到接触焊盘并在半导体器件的有源表面上延伸的第一PPI线。 UBM层形成在第一PPI线上并电连接到第一PPI线。密封环结构围绕模具上的半导体器件的上周围延伸。密封环结构包括在与第一PPI线和UBM层中的至少一个相同的高度上延伸的密封层。制造WLCSP的方法包括通过在模制的半导体器件上同时形成互连线和密封层来形成再布线层压结构。

3. 发明授权

US08217499B2 Structure to reduce etching residue 有权
标题翻译：结构减少蚀刻残留
公开(公告)号：US08217499B2
公开(公告)日：2012-07-10
申请号：US12952485
申请日：2010-11-23
申请人： Tsung-Yuan Yu , Hsien-Wei Chen , Chung-Ying Yang
发明人： Tsung-Yuan Yu , Hsien-Wei Chen , Chung-Ying Yang
IPC分类号： H01L23/544
CPC分类号： H01L21/31144 , H01L21/32139 , H01L23/585 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.
摘要翻译：描述了用于减少部分蚀刻的材料的结构。该结构包括两个沟槽之间的交叉区域的布局。首先，具有梯形角的大交叉区域可以用两个沟槽之间的正交交替来代替。布局减少了交叉区域以及在交叉区域留下部分蚀刻的材料的可能性。该结构还包括用未蚀刻的小梯形区域或多个未蚀刻的正方形区域填充交叉区域的替代方法，使得交点处的开口面积减小，并且部分蚀刻材料的可能性降低太。

4. 发明申请

US20120126359A1 Structure to Reduce Etching Residue 有权
标题翻译：减少蚀刻残渣的结构
公开(公告)号：US20120126359A1
公开(公告)日：2012-05-24
申请号：US12952485
申请日：2010-11-23
申请人： Tsung-Yuan Yu , Hsien-Wei Chen , Chung-Ying Yang
发明人： Tsung-Yuan Yu , Hsien-Wei Chen , Chung-Ying Yang
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L21/31144 , H01L21/32139 , H01L23/585 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.
摘要翻译：描述了用于减少部分蚀刻的材料的结构。该结构包括两个沟槽之间的交叉区域的布局。首先，具有梯形角的大交叉区域可以用两个沟槽之间的正交交替来代替。布局减少了交叉区域以及在交叉区域留下部分蚀刻的材料的可能性。该结构还包括用未蚀刻的小梯形区域或多个未蚀刻的正方形区域填充交叉区域的替代方法，使得交点处的开口面积减小，并且部分蚀刻材料的可能性降低太。

5. 发明授权

US08581389B2 Uniformity control for IC passivation structure 有权
标题翻译： IC钝化结构均匀性控制
公开(公告)号：US08581389B2
公开(公告)日：2013-11-12
申请号：US13117641
申请日：2011-05-27
申请人： Hsien-Wei Chen , Tsung-Yuan Yu
发明人： Hsien-Wei Chen , Tsung-Yuan Yu
IPC分类号： H01L23/12 , H01L21/4763
CPC分类号： H01L23/522 , H01L23/3114 , H01L23/3171 , H01L23/525 , H01L24/13 , H01L2924/1305 , H01L2924/1306 , H01L2924/00
摘要： The present disclosure involves a semiconductor device. The semiconductor device includes a wafer containing an interconnect structure. The interconnect structure includes a plurality of vias and interconnect lines. The semiconductor device includes a first conductive pad disposed over the interconnect structure. The first conductive pad is electrically coupled to the interconnect structure. The semiconductor device includes a plurality of second conductive pads disposed over the interconnect structure. The semiconductor device includes a passivation layer disposed over and at least partially sealing the first and second conductive pads. The semiconductor device includes a conductive terminal that is electrically coupled to the first conductive pad but is not electrically coupled to the second conductive pads.
摘要翻译：本发明涉及半导体器件。半导体器件包括含有互连结构的晶片。互连结构包括多个通孔和互连线。半导体器件包括布置在互连结构上的第一导电焊盘。第一导电焊盘电耦合到互连结构。半导体器件包括布置在互连结构上的多个第二导电焊盘。半导体器件包括设置在第一和第二导电焊盘之上并且至少部分地密封第一和第二导电焊盘的钝化层。半导体器件包括电耦合到第一导电焊盘但不电耦合到第二导电焊盘的导电端子。

6. 发明申请

US20130140706A1 UBM Structures for Wafer Level Chip Scale Packaging 有权
标题翻译： UBM晶圆级芯片级封装结构
公开(公告)号：US20130140706A1
公开(公告)日：2013-06-06
申请号：US13312538
申请日：2011-12-06
申请人： Tsung-Yuan Yu , Hsien-Wei Chen , Ying-Ju Chen , Shih-Wei Liang
发明人： Tsung-Yuan Yu , Hsien-Wei Chen , Ying-Ju Chen , Shih-Wei Liang
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L24/11 , H01L23/3192 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/02166 , H01L2224/02375 , H01L2224/0401 , H01L2224/05005 , H01L2224/05008 , H01L2224/05022 , H01L2224/05124 , H01L2224/05541 , H01L2224/05552 , H01L2224/05572 , H01L2224/0603 , H01L2224/06131 , H01L2924/00014 , H01L2924/206 , H01L2924/00012
摘要： A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.
摘要翻译：晶片级芯片级半导体器件包括半导体管芯，第一下凸块金属结构和第二凸块下金属结构。具有第一外壳的第一下凸块金属结构形成在半导体管芯的拐角区域或边缘区域上。具有第二外壳的第二下凸块金属结构形成在半导体管芯的内部区域上。第一个外壳大于第二个外壳。

7. 发明授权

US09806042B2 Strain reduced structure for IC packaging 有权
公开(公告)号：US09806042B2
公开(公告)日：2017-10-31
申请号：US13448217
申请日：2012-04-16
申请人： Hsien-Wei Chen , Ying-Ju Chen , Tsung-Yuan Yu , Yu-Feng Chen , Tsung-Ding Wang
发明人： Hsien-Wei Chen , Ying-Ju Chen , Tsung-Yuan Yu , Yu-Feng Chen , Tsung-Ding Wang
IPC分类号： H01L33/48 , H01L23/00
CPC分类号： H01L24/06 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05008 , H01L2224/05541 , H01L2224/05548 , H01L2224/05552 , H01L2224/05567 , H01L2224/05569 , H01L2224/05572 , H01L2224/05644 , H01L2224/0603 , H01L2224/06131 , H01L2224/06133 , H01L2224/06179 , H01L2224/1134 , H01L2224/13005 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13166 , H01L2224/13181 , H01L2224/16145 , H01L2224/16238 , H01L2224/81191 , H01L2924/00014 , H01L2924/10253 , H01L2924/1306 , H01L2924/014 , H01L2924/00 , H01L2924/207 , H01L2924/206
摘要： A semiconductor device includes a semiconductor die having first and second conductive pads, and a substrate having third and fourth bonding pads. A width ratio of the first conductive pad over the third bonding pad at an inner region is different from a width ratio of the second conductive pad over the fourth bonding pad at an outer region.

8. 发明授权

US09099485B2 Methods and apparatus of guard rings for wafer-level-packaging 有权
标题翻译：晶圆级封装保护环的方法和装置
公开(公告)号：US09099485B2
公开(公告)日：2015-08-04
申请号：US13419126
申请日：2012-03-13
申请人： Tsung-Yuan Yu , Hsien-Wei Chen
发明人： Tsung-Yuan Yu , Hsien-Wei Chen
IPC分类号： H01L23/50 , H01L21/786 , H01L23/58 , H01L23/485 , H01L23/00
CPC分类号： H01L23/562 , H01L21/76877 , H01L22/32 , H01L23/3171 , H01L23/485 , H01L23/528 , H01L23/544 , H01L23/585 , H01L24/00 , H01L24/03 , H01L24/05 , H01L2223/5446 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05647 , H01L2224/131 , H01L2924/12042 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： Methods and apparatuses are disclosed for forming a post-passivation interconnect (PPI) guard ring over a circuit in a wafer forming a wafer level package (WLP). A circuit device comprises a guard ring and an active area. A passivation layer is formed on top of the circuit device over the guard ring and the active area, wherein the passivation layer contains a passivation contact connected to the guard ring. A first polymer layer is formed over the passivation layer. A PPI opening is formed within the first polymer layer or within the passivation layer over the passivation contact. A PPI guard ring is formed filling the PPI opening in touch with the passivation contact and extending on top of the first polymer layer or the passivation layer.
摘要翻译：公开了用于在形成晶片级封装（WLP）的晶片中的电路上形成钝化后互连（PPI）保护环的方法和装置。电路装置包括保护环和有源区。在保护环和有源区上的电路器件的顶部上形成钝化层，其中钝化层包含连接到保护环的钝化接触点。在钝化层上形成第一聚合物层。 PPI开口形成在第一聚合物层内或者在钝化层上方钝化接触。形成PPI保护环，填充与钝化接触相接触的PPI开口并在第一聚合物层或钝化层的顶部延伸。

9. 发明授权

US09000876B2 Inductor for post passivation interconnect 有权
标题翻译：后钝化互连电感
公开(公告)号：US09000876B2
公开(公告)日：2015-04-07
申请号：US13419272
申请日：2012-03-13
申请人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
发明人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
IPC分类号： H01F5/00 , H01F27/28 , H01F27/36 , H01L31/107 , H01L23/522 , H01L23/552 , H01L23/00 , H01L49/02 , H01L23/58
CPC分类号： H01L23/5227 , H01L21/768 , H01L23/5225 , H01L23/552 , H01L23/585 , H01L24/03 , H01L24/11 , H01L28/10 , H01L2224/02351 , H01L2224/0401 , H01L2224/06515 , Y10T29/4902
摘要： An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
摘要翻译：提供一种形成电感器件的电感器件和方法。在一些实施例中，电感器件包括设置在衬底上的后钝化互连（PPI）层和凸块下金属化（UBM）层。 PPI层形成线圈和虚拟垫。虚拟焊盘围绕线圈的大部分设置，以屏蔽线圈免受电磁干扰。 UBM层的第一部分电耦合到线圈并且被配置为与电耦合构件相接合。

10. 发明申请

US20130240883A1 Contact Test Structure and Method 有权
公开(公告)号：US20130240883A1
公开(公告)日：2013-09-19
申请号：US13422846
申请日：2012-03-16
申请人： Jie Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Ying-Ju Chen
发明人： Jie Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Ying-Ju Chen
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L22/34 , H01L22/30 , H01L22/32 , H01L23/4824 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05008 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05541 , H01L2224/05555 , H01L2224/05569 , H01L2224/05572 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/0603 , H01L2224/06179 , H01L2224/06505 , H01L2224/11015 , H01L2224/13006 , H01L2224/13022 , H01L2224/13026 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14153 , H01L2224/14155 , H01L2924/01029 , H01L2924/00014 , H01L2924/207 , H01L2924/014
摘要： A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

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