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1. 发明申请

US20110037633A1 DELTA SIGMA-TYPE A/D CONVERTER 有权
标题翻译： DELTA SIGMA型A / D转换器
公开(公告)号：US20110037633A1
公开(公告)日：2011-02-17
申请号：US12911286
申请日：2010-10-25
申请人： Toshio KUMAMOTO , Takashi Okuda , Tatsuo Sengoku , Akira Kitaguchi
发明人： Toshio KUMAMOTO , Takashi Okuda , Tatsuo Sengoku , Akira Kitaguchi
IPC分类号： H03M1/20
CPC分类号： H03M3/328 , H03M3/33 , H03M3/43 , H03M3/452
摘要： There is provided a technique for reducing the adverse effect of idle tones in the channels in a ΔΣ-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ΔΣ-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.
摘要翻译：提供了一种用于减少包括用于将模拟输入信号转换为数字信号的多个通道的＆Dgr＆amp; S型A / D转换器中的通道中的空闲音调的不利影响的技术。＆amp; S＆amp; S型A / D转换器包括用于将左模拟输入信号转换为数字信号的L通道和用于将右模拟输入信号转换为数字信号的R通道。 L沟道和R沟道中的每一个包括用于产生用于移动空闲频率的频率的DC附加电压的DC抖动电路。在L沟道和R沟道中，由DC抖动电路产生的直流相加电压彼此不同。

2. 发明授权

US07952506B2 ΔΣ-type A/D converter 有权
标题翻译：＆Dgr＆amp; S型A / D转换器
公开(公告)号：US07952506B2
公开(公告)日：2011-05-31
申请号：US12911286
申请日：2010-10-25
申请人： Toshio Kumamoto , Takashi Okuda , Tatsuo Sengoku , Akira Kitaguchi
发明人： Toshio Kumamoto , Takashi Okuda , Tatsuo Sengoku , Akira Kitaguchi
IPC分类号： H03M3/00
CPC分类号： H03M3/328 , H03M3/33 , H03M3/43 , H03M3/452
摘要： There is provided a technique for reducing the adverse effect of idle tones in the channels in a ΔΣ-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ΔΣ-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.
摘要翻译：提供了一种用于减少包括用于将模拟输入信号转换为数字信号的多个通道的＆Dgr＆amp; S型A / D转换器中的通道中的空闲音调的不利影响的技术。＆amp; S＆amp; S型A / D转换器包括用于将左模拟输入信号转换为数字信号的L通道和用于将右模拟输入信号转换为数字信号的R通道。 L沟道和R沟道中的每一个包括用于产生用于移动空闲频率的频率的DC附加电压的DC抖动电路。在L沟道和R沟道中，由DC抖动电路产生的直流相加电压彼此不同。

3. 发明授权

US07847714B2 ΔΣ-type A/D converter 有权
标题翻译：＆Dgr＆amp; S型A / D转换器
公开(公告)号：US07847714B2
公开(公告)日：2010-12-07
申请号：US12411142
申请日：2009-03-25
申请人： Toshio Kumamoto , Takashi Okuda , Tatsuo Sengoku , Akira Kitaguchi
发明人： Toshio Kumamoto , Takashi Okuda , Tatsuo Sengoku , Akira Kitaguchi
IPC分类号： H03M1/20
CPC分类号： H03M3/328 , H03M3/33 , H03M3/43 , H03M3/452
摘要： There is provided a technique for reducing the adverse effect of idle tones in the channels in a ΔΣ-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ΔΣ-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.
摘要翻译：提供了一种用于减少包括用于将模拟输入信号转换为数字信号的多个通道的＆Dgr＆amp; S型A / D转换器中的通道中的空闲音调的不利影响的技术。＆amp; S＆amp; S型A / D转换器包括用于将左模拟输入信号转换为数字信号的L通道和用于将右模拟输入信号转换为数字信号的R通道。 L沟道和R沟道中的每一个包括用于产生用于移动空闲频率的频率的DC附加电压的DC抖动电路。在L沟道和R沟道中，由DC抖动电路产生的直流相加电压彼此不同。

4. 发明授权

US07557427B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07557427B2
公开(公告)日：2009-07-07
申请号：US11845339
申请日：2007-08-27
申请人： Takashi Okuda , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
发明人： Takashi Okuda , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
IPC分类号： H01L51/05
CPC分类号： H01L23/5223 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
摘要翻译：半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

5. 发明授权

US06809582B2 Semiconductor device including a differential transistor pair 失效
标题翻译：包括差分晶体管对的半导体器件
公开(公告)号：US06809582B2
公开(公告)日：2004-10-26
申请号：US10615932
申请日：2003-07-10
申请人： Yasuo Morimoto , Toshio Kumamoto , Takashi Okuda
发明人： Yasuo Morimoto , Toshio Kumamoto , Takashi Okuda
IPC分类号： G06G712
CPC分类号： H01L27/0255 , H01L27/0203 , H03F1/523 , H03F2200/444 , H03F2203/45568 , H03K5/2481
摘要： Two groups of diodes are connected to internal lines transmitting complementary signals, respectively, and positions of the centers of gravity of the groups of diodes are made coincident with each other. A circuit capable of preventing the deviation of the characteristics of differential transistor pair caused by an antenna effect and highly immune against a substrate noise can be achieved.
摘要翻译：两组二极管分别连接到传输互补信号的内部线路，并且二极管组的重心位置彼此一致。可以实现能够防止由天线效应引起的差分晶体管对的特性偏离并且高度免于衬底噪声的电路。

6. 发明授权

US06734816B2 D/A converter with high jitter resistance 有权
标题翻译： D / A转换器具有高抖动电阻
公开(公告)号：US06734816B2
公开(公告)日：2004-05-11
申请号：US10408238
申请日：2003-04-08
申请人： Yasuo Morimoto , Toshio Kumamoto , Takashi Okuda
发明人： Yasuo Morimoto , Toshio Kumamoto , Takashi Okuda
IPC分类号： H03M166
CPC分类号： H03M3/372 , H03M3/502
摘要： A D/A converter including a plurality of potential generating sections. They each receive a 1-bit signal from one of an input terminal and delay circuit, and a clock signal or inverted clock signal from an input section or inverter for inverting the clock signal. When the clock signal or inverted clock signal is at a first signal level, they generate a first reference potential or second reference potential in response to the signal level of the 1-bit signal. When the clock signal or inverted clock signal is at the second level, they generate an intermediate potential between the first and second reference potentials. The potentials generated by the plurality of potential generating sections are combined by a combining section. The D/A converter can improve resistance to jitter, and to simplify the configuration of a post-stage filter circuit.
摘要翻译：一种D / A转换器，包括多个电位产生部分。它们各自从输入端和延迟电路之一接收1位信号，以及来自用于反相时钟信号的输入部分或反相器的时钟信号或反相时钟信号。当时钟信号或反相时钟信号处于第一信号电平时，它们响应于1位信号的信号电平而产生第一参考电位或第二参考电位。当时钟信号或反相时钟信号处于第二电平时，它们在第一和第二参考电位之间产生中间电位。由多个电位产生部分产生的电位由组合部分组合。 D / A转换器可以提高抗抖动性，并简化后级滤波电路的配置。

7. 发明授权

US09118341B2 Delta-sigma A/D converter 有权
标题翻译： Delta-sigma A / D转换器
公开(公告)号：US09118341B2
公开(公告)日：2015-08-25
申请号：US13523592
申请日：2012-06-14
申请人： Takashi Matsumoto , Toshio Kumamoto , Takashi Okuda
发明人： Takashi Matsumoto , Toshio Kumamoto , Takashi Okuda
IPC分类号： H03M1/20 , H03M3/00 , H03M1/00 , H03M1/06 , H03M1/12
CPC分类号： H03M3/332 , H03M1/00 , H03M1/0641 , H03M1/12 , H03M3/30 , H03M3/43 , H03M3/452 , H03M3/454
摘要： A delta-sigma A/D converter having plural input channels comprises a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.
摘要翻译：具有多个输入通道的Δ-ΣA / D转换器包括量化并输出接收信号的第一量化器; 第一D / A转换器，其将第一量化器的输出信号转换为模拟信号，并输出转换的模拟信号; 第一操作单元，其输出表示第一模拟输入信号和第一D / A转换器的输出信号的差的信号; 第一积分器，其对第一操作单元的输出信号进行积分并输出积分信号; 产生第一抖动信号的第一抖动电路; 以及第二操作单元，其将第一抖动信号添加到第一积分器的输出信号，并将相加的信号输出到第一量化器。

8. 发明申请

US20090027247A1 A/D CONVERTER AND SEMICONDUCTOR DEVICE 失效
标题翻译： A / D转换器和半导体器件
公开(公告)号：US20090027247A1
公开(公告)日：2009-01-29
申请号：US12178244
申请日：2008-07-23
申请人： Toshio KUMAMOTO , Takashi Okuda
发明人： Toshio KUMAMOTO , Takashi Okuda
IPC分类号： H03M3/02 , H03M3/00
CPC分类号： H03M3/376 , H03M3/452
摘要： In an A/D converter including a switched capacitor integration circuit, to suppress an effect of a noise generated in the switched capacitor circuit while suppressing increase in a forming area of the circuit. A first-stage integrator of a differential input type A/D converter includes first and second switched capacitor circuits, and includes a noise cancel circuit for generating a noise cancel signal to cancel a kickback noise generated due to switching operation thereof.
摘要翻译：在包括开关电容器积分电路的A / D转换器中，抑制在开关电容器电路中产生的噪声的影响，同时抑制电路的形成区域的增加。差分输入型A / D转换器的第一级积分器包括第一和第二开关电容器电路，并且包括用于产生噪声消除信号的噪声消除电路，以消除由于其切换操作而产生的反冲噪声。

9. 发明授权

US07009539B2 Modulator providing only quantization error component to delta sigma modulator 有权
标题翻译：调制器只提供量化误差分量到ΔΣ调制器
公开(公告)号：US07009539B2
公开(公告)日：2006-03-07
申请号：US10715456
申请日：2003-11-19
申请人： Takashi Okuda , Toshio Kumamoto , Yasuo Morimoto
发明人： Takashi Okuda , Toshio Kumamoto , Yasuo Morimoto
IPC分类号： H03M3/00
CPC分类号： H03M3/46 , H03M3/418 , H03M3/454 , H03M3/50 , H03M7/3022 , H03M7/3028 , H03M7/304
摘要： A ΔΣ modulator modulates only an error component separated by a component separating portion. Therefore, even if the number of order of the ΔΣ modulator increases, an amplitude of an output of an integrator in the final stage does not excessively increase, and the stability of the modulator can be achieved. Since the signal component separated by the component separating portion does not pass through the ΔΣ modulator, an intensity of an input signal can be maintained as it is, and the modulator can have high precision.
摘要翻译： DeltaSigma调制器仅调制由分量分离部分分离的误差分量。因此，即使DeltaSigma调制器的次数增加，最终级的积分器的输出的幅度也不会过度增加，并且可以实现调制器的稳定性。由于由分量分离部分分离的信号分量不通过ΔΣ调制器，所以可以保持输入信号的强度，并且调制器可以具有高精度。

10. 发明授权

US08223050B2 Delta-sigma A/D converter 失效
标题翻译： Delta-sigma A / D转换器
公开(公告)号：US08223050B2
公开(公告)日：2012-07-17
申请号：US12911345
申请日：2010-10-25
申请人： Takashi Matsumoto , Toshio Kumamoto , Takashi Okuda
发明人： Takashi Matsumoto , Toshio Kumamoto , Takashi Okuda
IPC分类号： H03M1/20
CPC分类号： H03M3/332 , H03M1/00 , H03M1/0641 , H03M1/12 , H03M3/30 , H03M3/43 , H03M3/452 , H03M3/454
摘要： In a delta-sigma A/D converter provided with plural channels for converting an analog input signal into a digital signal, an adverse influence of an idle tone is reduced in each channel. The delta-sigma A/D converter comprises: a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.
摘要翻译：在具有用于将模拟输入信号转换为数字信号的多个通道的Δ-ΣA / D转换器中，在每个通道中降低了空闲音调的不利影响。 Δ-ΣA / D转换器包括：量化并输出接收信号的第一量化器; 第一D / A转换器，其将第一量化器的输出信号转换为模拟信号，并输出转换的模拟信号; 第一操作单元，其输出表示第一模拟输入信号和第一D / A转换器的输出信号的差的信号; 第一积分器，其对第一运算单元的输出信号进行积分并输出积分信号; 产生第一抖动信号的第一抖动电路; 以及第二操作单元，其将第一抖动信号添加到第一积分器的输出信号，并将相加的信号输出到第一量化器。

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