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1. 发明授权

US4734131A Permanent-magnetic material 失效
标题翻译：永磁材料
公开(公告)号：US4734131A
公开(公告)日：1988-03-29
申请号：US75996
申请日：1987-07-21
申请人： Tomohisa Arai , Naoyuki Sori , Seiki Sato , Nobuo Uchida
发明人： Tomohisa Arai , Naoyuki Sori , Seiki Sato , Nobuo Uchida
IPC分类号： H01F1/053 , C22C1/04 , C22C19/07 , C22C38/00 , C22C38/14 , F04B49/10 , H01F1/00 , H01F1/057 , H01F7/00 , C22C29/14
CPC分类号： H01F1/0577 , C22C1/0441 , H01F1/057
摘要： A permanent-magnet material having a composition represented by the following formula;R(Co.sub.1-X-Y-.alpha.-.beta. Fe.sub.X Cu.sub.Y M.sub..alpha. M'.sub.62)A(wherein X, Y, .alpha., .beta., and A respectively represent the following numbers:0.01.ltoreq.X, 0.02.ltoreq.Y.ltoreq.0.25, 0.001.ltoreq..alpha..ltoreq.0.15,0.0001.ltoreq..beta..ltoreq.0.001, and 6.0.ltoreq.A.ltoreq.8.3,providing that the amount of Fe to be added should be less than 15% by weight, based on the total amount of the composition, and R, M, and M' respectively represent the following constituents:R: At least one element selected from the group of rare earth elements,M: At least one element selected from the group consisting of Ti, Zr, Hf, Nb, V, and Ta, andM': B or B+Si),is disclosed. The permanent-magnetic material of the present invention is consisting of an intermetallic compound, permitting coexistence of liquid and solid phases in a wide region, and enabling sintering conditions warranting impartation of highly desirable magnetic characteristics to be selected in wide ranges.
摘要翻译：具有由下式表示的组成的永久磁铁材料; R（Co1-XY-α-βFeXCuYMαM'62）A（其中X，Y，α，β和A分别表示以下数字：0.01

2. 发明授权

US5509136A Data processing system including different throughput access sources accessing main storage in same direction 失效
标题翻译：数据处理系统包括不同的吞吐量访问源，以相同方向访问主存储
公开(公告)号：US5509136A
公开(公告)日：1996-04-16
申请号：US357147
申请日：1994-12-15
申请人： Kenji Korekata , Nobuo Uchida
发明人： Kenji Korekata , Nobuo Uchida
IPC分类号： G06F12/06 , G06F13/18 , G06F15/17
CPC分类号： G06F13/18
摘要： A data processing system including a small throughput access source and a large throughput access source therein for accessing a main storage unit in a consecutive block access mode. The system further includes a detecting unit and a selecting unit. The detecting unit detects an access conflict expected to occur at the same address of the main storage unit. The selecting unit responds to the detection by the detecting unit and momentarily stops the access by the small throughput access source to give priority to the large throughput access source for accessing the conflicting address of the main storage unit.
摘要翻译：一种数据处理系统，包括小吞吐量访问源和其中的大量吞吐量访问源，用于以连续块访问模式访问主存储单元。该系统还包括检测单元和选择单元。检测单元检测预期在主存储单元的相同地址发生的访问冲突。选择单元响应于检测单元的检测，并且暂时停止小吞吐量访问源的访问以优先考虑用于访问主存储单元的冲突地址的大吞吐量访问源。

3. 发明授权

US5073871A Main storage access priority control system that checks bus conflict condition and logical storage busy condition at different clock cycles 失效
标题翻译：主要存储访问优先控制系统，在不同的时钟周期内检查总线冲突条件和逻辑存储繁忙条件
公开(公告)号：US5073871A
公开(公告)日：1991-12-17
申请号：US246087
申请日：1988-09-19
申请人： Nobuo Uchida , Yuji Oinaga , Mikio Itoh
发明人： Nobuo Uchida , Yuji Oinaga , Mikio Itoh
IPC分类号： G06F13/18
CPC分类号： G06F13/18
摘要： An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage. The system includes a first access request port unit for holding at least temporarily a segment address of the storage access requests from the processor; a first control unit responsive to the output of the first access request port unit for checking bus conflict conditions and prohibition conditions for a destination storage segment determined by the address of the storage access request; a second access request port unit responsive to the output of the first control unit for holding at least temporarily an intra-segment address of the storage access request; and a second control unit responsive to the output of the second access request port unit for checking logical storage busy conditions in the storage segments.

4. 发明授权

US07486754B2 System clock distributing apparatus and system clock distributing method 失效
标题翻译：系统时钟分配装置和系统时钟分配方法
公开(公告)号：US07486754B2
公开(公告)日：2009-02-03
申请号：US11116392
申请日：2005-04-28
申请人： Nobuo Uchida
发明人： Nobuo Uchida
IPC分类号： H04L7/00
CPC分类号： G06F1/04 , G06F1/06 , G06F1/10
摘要： To provide a system clock distributing apparatus and a system clock distributing method for reducing a skew of a system clock and a synchronizing signal at low cost. The system clock distributing apparatus for matching the timing of data by using the synchronizing signal includes an oscillator 1 that generates a periodical synchronizing signal and a PLL 2, a memory that stores the data, at least one CPU 13 that conducts a computing process using the data stored in the memory, at least one MAC 14 that controls an access from the CPU 13 to the memory, and at least one NB 12 that generates the system clock having a frequency that is an integral multiple of the synchronizing signal, and controls the CPU 13 and the MAC 14 based on the operation by the system clock.
摘要翻译：提供一种用于以低成本减少系统时钟和同步信号的偏斜的系统时钟分配装置和系统时钟分配方法。用于通过使用同步信号来匹配数据定时的系统时钟分配装置包括产生周期性同步信号的振荡器1和PLL 2，存储数据的存储器，至少一个CPU 13，其使用存储在存储器中的数据，至少一个MAC 14，其控制从CPU 13到存储器的访问;以及至少一个生成具有作为同步信号的整数倍的频率的系统时钟的NB 12，并且控制 CPU 13和MAC 14基于系统时钟的操作。

5. 发明申请

US20060153325A1 System clock distributing apparatus and system clock distributing method 失效
公开(公告)号：US20060153325A1
公开(公告)日：2006-07-13
申请号：US11116392
申请日：2005-04-28
申请人： Nobuo Uchida
发明人： Nobuo Uchida
IPC分类号： H04L7/00
CPC分类号： G06F1/04 , G06F1/06 , G06F1/10
摘要： To provide a system clock distributing apparatus and a system clock distributing method for reducing a skew of a system clock and a synchronizing signal at low cost. The system clock distributing apparatus for matching the timing of data by using the synchronizing signal includes an oscillator 1 that generates a periodical synchronizing signal and a PLL 2, a memory that stores the data, at least one CPU 13 that conducts a computing process using the data stored in the memory, at least one MAC 14 that controls an access from the CPU 13 to the memory, and at least one NB 12 that generates the system clock having a frequency that is an integral multiple of the synchronizing signal, and controls the CPU 13 and the MAC 14 based on the operation by the system clock.

6. 发明授权

US5214769A Multiprocessor control system 失效
标题翻译：多处理器控制系统
公开(公告)号：US5214769A
公开(公告)日：1993-05-25
申请号：US760821
申请日：1991-09-17
申请人： Nobuo Uchida , Yasuhiro Kuroda , Shoji Nakatani
发明人： Nobuo Uchida , Yasuhiro Kuroda , Shoji Nakatani
IPC分类号： G06F13/16
CPC分类号： G06F13/1657
摘要： A multiprocessor control system which has at least one main storage unit, a plurality of main storage control units, a plurality of processing units, and a control bus. Each processing unit is connected to the main storage unit through one of the main storage control units. When each processing unit transmits a request for access to at least one main storage unit, the processing units transmit the request to the main storage control units to which each processing unit is connected, and simultaneously, to all of the other main storage control units, through the control bus. All of the main storage control units process the request from the processing unit, synchronously, and execute a busy check control or the like. Data transmitted between each processing unit and an arbitrary one of the main storage units is transmitted only through the main storage control unit to which the processing unit is connected. By using this system, if units needing a high throughput are applied, the system can be controlled in a comparatively simple manner.
摘要翻译：一种具有至少一个主存储单元，多个主存储控制单元，多个处理单元和控制总线的多处理器控制系统。每个处理单元通过主存储控制单元之一连接到主存储单元。当每个处理单元发送对至少一个主存储单元的访问请求时，处理单元将该请求发送到连接有每个处理单元的主存储控制单元，并且同时向所有其他主存储控制单元发送，通过控制总线。所有主存储控制单元处理来自处理单元的请求，同步地执行繁忙的检查控制等。在每个处理单元和主存储单元中的任意一个之间传送的数据仅通过与处理单元连接的主存储控制单元进行传送。通过使用该系统，如果应用需要高吞吐量的单元，则可以以比较简单的方式控制系统。

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