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1. 发明授权

US07443222B1 Dynamic clock control 有权
标题翻译：动态时钟控制
公开(公告)号：US07443222B1
公开(公告)日：2008-10-28
申请号：US11753531
申请日：2007-05-24
申请人： Timothy Saxe , Senani Gunaratna , Stephen U. Yao
发明人： Timothy Saxe , Senani Gunaratna , Stephen U. Yao
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： An implementation of an apparatus and method to generate a dynamically controlled clock is provided. The resulting clock reduces otherwise produced narrow clock pulses and allows for control from two separate control signals. A first control signal indicates a low power mode, for example a chip-wide low power mode. A second control signal indicates a user-selected mode to shutdown a selected clock.
摘要翻译：提供了一种用于生成动态控制时钟的装置和方法的实现。所产生的时钟减少了另外产生的窄时钟脉冲，并允许从两个单独的控制信号进行控制。第一控制信号表示低功率模式，例如芯片级的低功率模式。第二控制信号指示用户选择的关闭所选时钟的模式。

2. 发明授权

US5436801A Method and structure for routing power for optimum cell utilization with two and three level metal in a partially predesigned integrated circuit 失效
标题翻译：用于在部分预先设计的集成电路中利用两个和三个金属级别来优化单元利用的路由功率的方法和结构
公开(公告)号：US5436801A
公开(公告)日：1995-07-25
申请号：US120148
申请日：1993-09-09
申请人： Tushar Gheewala , Rustam Mehta , Timothy Saxe
发明人： Tushar Gheewala , Rustam Mehta , Timothy Saxe
IPC分类号： H01L23/528 , H01R9/00
CPC分类号： H01L23/5286 , H01L2924/0002
摘要： An integrated circuit structure which employs at least two metal levels overlying an array of circuit elements. Each metal level contains signal routing resources which can be used for supplying power and interconnecting circuit elements. The metal levels include a first metal level directly overlying the array of circuit elements, intermediate metal levels (if there are more than two metal levels), and a top metal level overlying all other metal levels. Power carrying tracks are disposed in the top metal level. Power antennae are disposed in the first metal level, but only where necessary to provide power to the circuit elements. The power antennae are for connecting the power carrying tracks to the circuit elements. Power bridges are disposed in intermediate metal levels between the first metal level and the top metal level. The power bridges are for connecting the power carrying tracks to the power antennae. Contacts to the first metal level are used as a means by which the power antennae are connected to the circuit elements. Vias to the metal levels overlying the first metal level are used as a means by which the power carrying tracks are connected to the power bridges and the power antennae, and by which the power bridges are connected to other power bridges and the power antennae.
摘要翻译：一种集成电路结构，其采用覆盖电路元件阵列的至少两个金属电平。每个金属层包含可用于供电和互连电路元件的信号路由资源。金属水平包括直接覆盖电路元件阵列的第一金属水平，中间金属水平（如果存在多于两个金属水平）以及覆盖所有其它金属水平的顶部金属水平。电力承载轨道设置在顶部金属水平面上。功率天线设置在第一金属级，但仅在必要时向电路元件供电。功率天线用于将电力承载轨道连接到电路元件。功率桥被布置在第一金属层与顶层金属层之间的中间金属层。电源桥用于将电力传输轨道连接到电源天线。与第一金属电平的接触被用作电力天线连接到电路元件的手段。使用覆盖在第一金属层上的金属层的通路用作电力承载轨道连接到电力桥和功率天线的装置，并且电力桥连接到其它电力桥和功率天线。

3. 发明授权

US06272655B1 Method of reducing test time for NVM cell-based FPGA 失效
标题翻译：降低NVM单元FPGA测试时间的方法
公开(公告)号：US06272655B1
公开(公告)日：2001-08-07
申请号：US09096142
申请日：1998-06-11
申请人： Volker Hecht , Timothy Saxe
发明人： Volker Hecht , Timothy Saxe
IPC分类号： G01R3128
CPC分类号： G01R31/318519
摘要： The present invention provides for a method of testing an FPGA using NVM memory cells for programmable interconnects. The NVM memory cells are arranged as a memory array of rows and columns. User-configurable logic elements and interconnections, which are programmed by the stored states of the memory cells, are organized into identical and/or differing tiles. The tiles are organized into an array of rows and columns superimposed upon the memory array. The testing method includes: selecting test circuit configurations by which identical tiles are identically programmed as much as possible; and simultaneously programming and simultaneously erasing pluralities of the memory rows corresponding to the tiles into the test circuit configurations. Additionally, the test circuit configurations programmed into the FPGA are tested at a lower supply voltage than that of normal operation. Programming is performed at reduced programming and erasing pulse voltages and times by substantially ignoring retention and disturb effect margin amounts for the NVM memory cells. In this manner, the time for testing the FPGA is considerably reduced.
摘要翻译：本发明提供了一种使用用于可编程互连的NVM存储器单元测试FPGA的方法。 NVM存储单元被排列成行和列的存储器阵列。由存储器单元的存储状态编程的用户可配置的逻辑元件和互连被组织成相同和/或不同的瓦片。瓦片被组织成叠加在存储器阵列上的行和列阵列。测试方法包括：选择测试电路配置，通过该配置尽可能相同地编程相同的瓦片; 并且同时编辑并同时擦除对应于瓦片的多个存储器行到测试电路配置中。此外，编程到FPGA中的测试电路配置在比正常操作更低的电源电压下进行测试。通过基本上忽略NVM存储器单元的保留和干扰效应余量来减少编程和擦除脉冲电压和时间的编程。以这种方式，大大减少了测试FPGA的时间。

4. 发明授权

US5594363A Logic cell and routing architecture in a field programmable gate array 失效
标题翻译：现场可编程门阵列中的逻辑单元和路由架构
公开(公告)号：US5594363A
公开(公告)日：1997-01-14
申请号：US418972
申请日：1995-04-07
申请人： Richard D. Freeman , Joseph D. Linoff , Timothy Saxe
发明人： Richard D. Freeman , Joseph D. Linoff , Timothy Saxe
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704
摘要： The present invention provides for an FPGA integrated circuit having an array of logic cells and interconnect lines interconnected by programmable switches, each formed from a nonvolatile memory cell. The logic cell is designed to provide logic or memory functions according to the setting of programmable switches within the cell. The logic cells in the array are interconnectable by a hierarchy of local, long and global wiring segments. The interconnections are made by the setting of programmable switches between the wiring segments.
摘要翻译：本发明提供了一种FPGA集成电路，其具有由非易失性存储单元形成的可编程开关互连的逻辑单元和互连线阵列。逻辑单元被设计为根据单元内的可编程开关的设置来提供逻辑或存储器功能。阵列中的逻辑单元可通过本地，长和全局布线段的层次结构互连。互连通过布线段之间的可编程开关的设置来实现。

5. 发明授权

US4736338A Programmable look up system 失效
标题翻译：可编程查询系统
公开(公告)号：US4736338A
公开(公告)日：1988-04-05
申请号：US916128
申请日：1986-10-07
申请人： Timothy Saxe , Daniel R. Perkins
发明人： Timothy Saxe , Daniel R. Perkins
IPC分类号： G06F17/50 , G06F9/44
CPC分类号： G06F17/5022
摘要： A simulation technique for modeling the function of logic elements containing memory is disclosed. The technique uses a table to represent the logical function of the devices that are being simulated.
摘要翻译：公开了一种用于对包含存储器的逻辑元件的功能建模的仿真技术。该技术使用表来表示正在被模拟的设备的逻辑功能。

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