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1. 发明申请

US20070123048A1 Use of a plasma source to form a layer during the formation of a semiconductor device 失效
公开(公告)号：US20070123048A1
公开(公告)日：2007-05-31
申请号：US11651158
申请日：2007-01-09
申请人： Thomas Figura , Kevin Donohoe , Thomas Dunbar
发明人： Thomas Figura , Kevin Donohoe , Thomas Dunbar
IPC分类号： H01L21/311
CPC分类号： H01L21/312 , H01L21/02129 , H01L21/32139 , H01L21/76865 , H01L28/40 , H01L28/60
摘要： A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

2. 发明申请

US20060194437A1 Use of pulsed grounding source in a plasma reactor 审中-公开
公开(公告)号：US20060194437A1
公开(公告)日：2006-08-31
申请号：US11405979
申请日：2006-04-18
申请人： Chuck Hedberg , Kevin Donohoe
发明人： Chuck Hedberg , Kevin Donohoe
IPC分类号： C23F1/00 , H01L21/306 , H01L21/302
CPC分类号： H01J37/32623 , H01J37/32706 , H01J37/32935 , H01L21/3065 , H01L21/31116
摘要： A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental effects of feature charging during the operation of a plasma reactor.

3. 发明授权

US06280646B1 Use of a chemically active reticle carrier for photomask etching 失效
标题翻译：使用化学活性掩模版载体进行光掩模蚀刻
公开(公告)号：US06280646B1
公开(公告)日：2001-08-28
申请号：US09354303
申请日：1999-07-16
申请人： Richard Stocks , Kevin Donohoe
发明人： Richard Stocks , Kevin Donohoe
IPC分类号： G03F712
CPC分类号： G03F7/427 , G03F1/80
摘要： A method and apparatus for improving etch uniformity in reticle etching by eliminating local effects at the edge of the reticle is disclosed. The present invention relates to a reticle frame which surrounds the reticle. The reticle frames are patterned with a pattern profile similar to that of the reticle to prevent edge uniformities of the reticle by allowing uniform plasma etching of the entire reticle surface. The reticle frames may also be used to move the reticle in and out of etch chambers without damaging them.
摘要翻译：公开了一种通过消除掩模版边缘的局部效应来改进掩模版蚀刻中的蚀刻均匀性的方法和装置。本发明涉及一种围绕着标线的标线框架。通过允许对整个标线片表面进行均匀的等离子体蚀刻，将掩模版框架图案化为与掩模版的图案相似，以防止标线片的边缘均匀性。标线框架也可用于将掩模版移入和移出蚀刻室，而不会损坏它们。

4. 发明申请

US20050173376A1 Method for etching a wafer in a plasma etch reactor 审中-公开
标题翻译：在等离子体蚀刻反应器中蚀刻晶片的方法
公开(公告)号：US20050173376A1
公开(公告)日：2005-08-11
申请号：US11101730
申请日：2005-04-08
申请人： Kevin Donohoe
发明人： Kevin Donohoe
IPC分类号： H01J37/32 , B44C1/22
CPC分类号： H01J37/32082 , H01J37/32623 , H01J37/32642 , Y10S156/915
摘要： This invention is a hardware modification which permits greater uniformity of etching to be achieved in a high-density-source plasma reactor (i.e., one which uses a remote source to generate a plasma, and which also uses high-frequency bias power on the wafer chuck). The invention addresses the uniformity problem which arises as the result of nonuniform power coupling between the wafer and the walls of the etch chamber. The solution to greatly mitigate the nonuniformity problem is to increase the impedance between the wafer and the chamber walls. This may be accomplished by placing a cylindrical dielectric wall around the wafer. Quartz is a dielectric material that is ideal for the cylindrical wall if silicon is to be etched selectively with respect to silicon dioxide, as quartz it is virtually inert under such conditions.
摘要翻译：本发明是一种硬件修改，其允许在高密度源等离子体反应器（即，使用远程源产生等离子体并且还在晶片上使用高频偏置功率的等离子体反应器）中实现更高的蚀刻均匀性卡盘）。本发明解决了由于晶片和蚀刻室的壁之间的不均匀功率耦合而产生的均匀性问题。大大减轻不均匀性问题的解决方案是增加晶片和室壁之间的阻抗。这可以通过在晶片周围放置圆柱形介电壁来实现。石英是一种电介质材料，对于圆柱形壁而言，如果要在二氧化硅上选择性地蚀刻硅，石英是在这种条件下实际上是惰性的。

5. 发明授权

US06402886B2 Use of a chemically active reticle carrier for photomask etching 失效
标题翻译：使用化学活性掩模版载体进行光掩模蚀刻
公开(公告)号：US06402886B2
公开(公告)日：2002-06-11
申请号：US09903559
申请日：2001-07-13
申请人： Richard Stocks , Kevin Donohoe
发明人： Richard Stocks , Kevin Donohoe
IPC分类号： H05H100
CPC分类号： G03F7/427 , G03F1/80
摘要： A method and apparatus for improving etch uniformity in reticle etching by eliminating local effects at the edge of the reticle is disclosed. The present invention relates to a reticle frame which surrounds the reticle. The reticle frames are patterned with a pattern profile similar to that of the reticle to prevent edge uniformities of the reticle by allowing uniform plasma etching of the entire reticle surface. The reticle frames may also be used to move the reticle in and out of etch chambers without damaging them.
摘要翻译：公开了一种通过消除掩模版边缘的局部效应来改进掩模版蚀刻中的蚀刻均匀性的方法和装置。本发明涉及一种围绕着标线的标线框架。通过允许对整个标线片表面进行均匀的等离子体蚀刻，将掩模版框架图案化为与掩模版的图案相似，以防止标线片的边缘均匀性。标线框架也可用于将掩模版移入和移出蚀刻室，而不会损坏它们。

6. 发明申请

US20060186087A1 Etchant and method of use 审中-公开
标题翻译：蚀刻剂和使用方法
公开(公告)号：US20060186087A1
公开(公告)日：2006-08-24
申请号：US11413501
申请日：2006-04-28
申请人： Kevin Donohoe , David Becker
发明人： Kevin Donohoe , David Becker
IPC分类号： B44C1/22
CPC分类号： H01L21/76897 , C09K13/08 , H01L21/31116 , H01L21/76802
摘要： A method of anisotropically etching a semiconductive substrate uses a hydrofluorocarbon etch gas with an etch selectivity fluorocarbon gas. The fluorocarbon gas is used under conditions that enhance selectivity of the etch to an etch stop layer with respect to a bulk dielectric material such as doped or undoped silicon dioxide. In one method, a silicon dioxide dielectric layer is provided upon an etch stop layer, wherein the etch stop layer comprises silicon dioxide that is doped differently from the silicon dioxide dielectric layer. A gaseous etchant including a hydrofluorocarbon etch gas and a fluorocarbon selectivity compound is provided, and the silicon dioxide dielectric layer is exposed to the gaseous etchant.
摘要翻译：各向异性蚀刻半导体衬底的方法使用具有蚀刻选择性碳氟化合物气体的氢氟烃蚀刻气体。碳氟化合物气体在相对于诸如掺杂或未掺杂的二氧化硅的体电介质材料增强蚀刻停止层的蚀刻选择性的条件下使用。在一种方法中，在蚀刻停止层上提供二氧化硅介电层，其中蚀刻停止层包括与二氧化硅介电层不同地掺杂的二氧化硅。提供了包括氢氟烃蚀刻气体和氟碳选择性化合物的气体蚀刻剂，并且将二氧化硅介电层暴露于气体蚀刻剂。

7. 发明申请

US20060105577A1 Aspect ratio controlled etch selectivity using time modulated DC bias voltage 审中-公开
标题翻译：使用时间调制DC偏置电压的长宽比控制蚀刻选择性
公开(公告)号：US20060105577A1
公开(公告)日：2006-05-18
申请号：US11319402
申请日：2005-12-29
申请人： Kevin Donohoe , Mirzafer Abatchev , Robert Veltrop
发明人： Kevin Donohoe , Mirzafer Abatchev , Robert Veltrop
IPC分类号： H01L21/302 , H01L29/00
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/31144 , H01L21/76804 , H01L21/76816 , H01L21/823425 , H01L21/823475
摘要： A modulated bias power etching method for etching a substrate is disclosed. The method alternatively deposits and etches material from a low aspect area of an integrated circuit device to form a static area while etching material from a high aspect area. The modulation pulse period and repetition rate are adjusted to permit deposition at low aspect ratio and very little or no deposition at high aspect ratio during the deposition cycle and to permit etching of the material deposited on the low aspect ratio area and etching of the material in the high aspect ratio area during the etching cycle.
摘要翻译：公开了一种用于蚀刻衬底的调制偏压功率蚀刻方法。该方法交替地从集成电路器件的低方面区域沉积和蚀刻材料，以在从高方面区域蚀刻材料的同时形成静态区域。调制脉冲周期和重复频率被调节以允许在低纵横比下进行沉积，并且在沉积周期期间在高纵横比下很少或没有沉积，并允许蚀刻沉积在低纵横比区域上的材料和蚀刻材料在蚀刻循环期间的高纵横比面积。

8. 发明授权

US5225024A Magnetically enhanced plasma reactor system for semiconductor processing 失效
标题翻译：用于半导体加工的磁加强等离子体反应堆系统
公开(公告)号：US5225024A
公开(公告)日：1993-07-06
申请号：US750720
申请日：1991-08-22
申请人： Peter R. Hanley , Stephen E. Savas , Karl B. Levy , Neeta Jha , Kevin Donohoe
发明人： Peter R. Hanley , Stephen E. Savas , Karl B. Levy , Neeta Jha , Kevin Donohoe
IPC分类号： H01J37/32 , H05H1/46
CPC分类号： H01J37/32623 , H01J37/3266 , H05H1/46
摘要： Magnetic confinement of electrons in a plasma reactor is effected using electro-magnetic coils and other magnets which generate respective magnetic fields which are mutually opposed and substantially orthogonal on their common axis to the major plane of a wafer being processed, instead of being aligned and parallel to the major plane as in prior magnetically enhanced plasma reactors. The respective magnetic fields combine to yield a net magnetic field which is nearly parallel to the wafer away from the magnetic axis so that electrons are confined in the usual manner. In addition, a magnetic mirror provides confinement near the magnetic axis. The E.times.B cross product defines a circumferential drift velocity urging electrons about a closed path about the magnetic axis. The magnetic and cross-product forces on plasma electrons have a rotational symmetry which enhances reaction uniformity across the wafer; this contrasts with the prior art in which lateral drift velocity disturbs plasma symmetry and thus reaction uniformity. Furthermore, the disclosed field geometry permits stronger electron confinement which enhances plasma reaction rates.
摘要翻译：使用电磁线圈和其它磁体来实现等离子体反应器中的电子的限制，这些磁体产生各自的磁场，这些磁场在它们的公共轴线上相互对置并且基本上正交于被处理的晶片的主平面，而不是对准和平行到现有的磁增强等离子体反应器中的主平面。相应的磁场结合起来产生一个净磁场，该磁场几乎平行于离开磁轴的晶片，使得电子以通常的方式被限制。此外，磁镜在磁轴附近提供约束。 ExB交叉乘积定义围绕磁轴围绕闭合路径推动电子的周向漂移速度。等离子体电子的磁性和交叉积分力具有提高晶片反应均匀性的旋转对称性; 这与现有技术形成对比，其中横向漂移速度扰乱等离子体对称性并因此干扰反应均匀性。此外，所公开的场几何形式允许更强的电子限制，这增强了等离子体反应速率。

9. 发明申请

US20060154483A1 METHOD OF PROVIDING A STRUCTURE USING SELF-ALIGNED FEATURES 审中-公开
标题翻译：使用自对准特征提供结构的方法
公开(公告)号：US20060154483A1
公开(公告)日：2006-07-13
申请号：US11277340
申请日：2006-03-23
申请人： Dinesh Chopra , Kevin Donohoe , Cem Basceri
发明人： Dinesh Chopra , Kevin Donohoe , Cem Basceri
IPC分类号： H01L21/44
CPC分类号： H01L21/28079 , H01L21/2885 , H01L21/3212 , H01L21/7684 , H01L21/76879 , H01L28/91 , H01L29/66583
摘要： In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the decrease in the isotropic flux of neutrals toward the bottom of the trench. Copper is subsequently electroplated. Because the seed layer is exposed only within the trench, copper deposits only therein. The self-aligned mask prevents plating outside of the trench. A chemical-mechanical planarization step removes the mask and the seed layer extending beyond the trench, leaving a copper structure within the trench. The structure may serve as a conductive line, an interconnect, or a capacitor plate.
摘要翻译：在镀铜工艺中，种子层均匀地沉积在表面上，包括衬里由该表面限定的高纵横比的沟槽。使用不能沉积在沟槽中的工艺来提供掩模层。在一个示例性实施例中，故障是由于中性粒子向沟槽底部的各向同性通量的减小。随后电镀铜。因为种子层仅在沟槽内露出，所以铜仅沉积在其中。自对准面罩可防止沟槽外的电镀。化学机械平面化步骤去除掩模和种子层延伸超过沟槽，在沟槽内留下铜结构。该结构可以用作导线，互连或电容器板。

10. 发明申请

US20050230048A1 Liner for use in processing chamber 审中-公开
标题翻译：衬板用于加工室
公开(公告)号：US20050230048A1
公开(公告)日：2005-10-20
申请号：US11149226
申请日：2005-06-10
申请人： Kevin Donohoe
发明人： Kevin Donohoe
IPC分类号： C23F1/00 , H01J37/32 , H01L21/00
CPC分类号： H01J37/32477 , H01J37/321 , H01J37/32458 , H01J37/32623 , H01L21/67069 , H01L21/6719
摘要： A container for use in a processing chamber to lessen the amount of contaminant particles found within the chamber after processing. The container fits closely within the chamber and includes ports for a gas conduit and a vacuum conduit. The container may be locked to the chamber through a locking mechanism and a recess in the container. The container may be guided into the chamber with a plurality of chamfers. The container may be used in inductively coupled plasma chambers, electron cyclotron resonance chambers, and chambers capable of receiving microwaves.
摘要翻译：一种用于处理室的容器，用于减少加工后在室内发现的污染物颗粒的量。容器紧密地配合在腔室内并且包括用于气体导管和真空导管的端口。容器可以通过锁定机构和容器中的凹部而被锁定到腔室。容器可以用多个倒角引导到腔室中。容器可用于感应耦合等离子体室，电子回旋共振室和能够接收微波的室。

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