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    • 3. 发明授权
    • Transmitting apparatus with bit arrangement method
    • 带排列方式的发送装置
    • US07860186B2
    • 2010-12-28
    • US10899068
    • 2004-07-27
    • Tetsuya YanoKazuhisa ObuchiShunji Miyazaki
    • Tetsuya YanoKazuhisa ObuchiShunji Miyazaki
    • H04L27/36
    • H04L27/3488H03M13/25H03M13/2957H04L1/0041H04L1/0057H04L1/0067H04L1/16
    • A transmitting apparatus comprising circuitry operable to generate a plurality of bit sequences using bits included in a first data block and a second data block, circuitry operable to control the plurality of bit sequences to correspond to a signal point on the phase plane, comprising a bit sequence generating unit operable to control the generation of the bit sequences to adjust an occupation rate occupied with predetermined bits included in the first data block to be closer to an occupation rate occupied with predetermined bits included in the second data block in regard to bit positions of the predetermined bits, based on an error tolerance of the respective bit sequences generated resulting from the correspondence to a signal point on the phase plane, and circuitry operable to transmit the signals obtained by multi-level modulations in accordance with each signal point.
    • 一种发送装置,包括可操作以使用包括在第一数据块和第二数据块中的比特来生成多个比特序列的电路,所述电路可操作以控制所述多个比特序列以对应于所述相位平面上的信号点,包括比特 序列产生单元,其可操作以控制比特序列的生成,以调整占据第一数据块中包含的预定比特占有率的占有率,以使其相对于第二数据块中包含的预定比特占据的占用率更接近第 基于由与相位平面上的信号点的对应产生的相应比特序列的误差容限,以及可操作以根据每个信号点发送通过多电平调制获得的信号的电路。
    • 4. 发明授权
    • Data receiving apparatus and hybrid-ARQ communication system
    • 数据接收装置和混合ARQ通信系统
    • US07500166B2
    • 2009-03-03
    • US11152902
    • 2005-06-15
    • Shunji MiyazakiKazuhisa ObuchiTetsuya Yano
    • Shunji MiyazakiKazuhisa ObuchiTetsuya Yano
    • G08C25/02H04L1/18
    • H04L1/1812H04L1/1819H04L1/1845H04L1/201
    • A receiver receives data transmitted from a transmitter. The data is stored in a buffer, and a reliability value of the data is computed by a computing unit. A determining unit determines reliability of the data by comparing a reliability value of existing data in the buffer and a reliability value of the data. When the reliability value of the data is higher than a predetermined value, the existing data is combined with the data. Then, an error correcting unit performs error correcting on combined data obtained, and outputs decoded bits. If the combined data includes many errors, retransmission of the data is requested to the transmitter. When the reliability value of the data is lower than the predetermined value, retransmission of data is directly requested without combining the data with the existing data.
    • 接收机接收从发射机发送的数据。 数据存储在缓冲器中,数据的可靠性值由计算单元计算。 确定单元通过比较缓冲器中现有数据的可靠性值和数据的可靠性值来确定数据的可靠性。 当数据的可靠性值高于预定值时,将现有数据与数据组合。 然后,错误校正单元对获得的组合数据执行纠错,并输出解码的比特。 如果组合数据包含许多错误,则向发射机请求数据的重传。 当数据的可靠性值低于预定值时,直接请求重发数据而不将数据与现有数据进行组合。
    • 7. 发明授权
    • Transmission device
    • 传输设备
    • US08234557B2
    • 2012-07-31
    • US13345969
    • 2012-01-09
    • Shunji MiyazakiKazuhisa ObuchiTetsuya Yano
    • Shunji MiyazakiKazuhisa ObuchiTetsuya Yano
    • G06F11/00H03M13/00
    • H03M13/2957H03M13/2903H03M13/635H03M13/653
    • A transmission device in a communication system where a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deletion of the dummy bits from the results of the systematic encoding is transmitted. The transmission device inserts dummy bits into information bits based on an interleaving pattern of an interleaving portion in a turbo encoder; performs systematic encoding of the information bits into which the dummy bits are inserted, and then deletes the dummy bits from the results of the systematic encoding to generate a systematic code; and transmits the systematic code. By considering the interleaving pattern, original bit positions, which, after interleaving, exists within the ranges of stipulated numbers of bits at the beginning and at the end, are determined in advance, and the dummy bit insertion portion executes control so as not to insert dummy bits into the original bit positions.
    • 发送通信系统中的发送装置,其中通过系统编码获得的系统代码,其中通过对其中插入有虚拟位的信息比特和通过从系统编码的结果中删除虚拟比特来发送。 传输设备基于turbo编码器中的交织部分的交织模式将伪比特插入到信息比特中; 执行插入虚拟位的信息位的系统编码,然后从系统编码的结果中删除虚拟位以产生系统代码; 并发送系统代码。 通过考虑交织模式,预先确定在交织之后存在于开始和结束的规定数量的范围内的原始位位置,并且虚拟位插入部分执行控制以便不插入 虚拟位进入原始位位置。
    • 8. 发明授权
    • Transmitting apparatus with bit arrangement method
    • 带排列方式的发送装置
    • US08213535B2
    • 2012-07-03
    • US12948341
    • 2010-11-17
    • Tetsuya YanoKazuhisa ObuchiShunji Miyazaki
    • Tetsuya YanoKazuhisa ObuchiShunji Miyazaki
    • H04L27/00
    • H04L27/3488H03M13/25H03M13/2957H04L1/0041H04L1/0057H04L1/0067H04L1/16
    • A method of transmitting data by transmitting apparatus, that includes controlling generation of bit sequences to adjust an occupation rate of systematic bits in a first data block including systematic bits and parity bits, which is obtained by encoding first data in a first encoding process, and is equal or closer to an occupation rate of systematic bits in a second data block including systematic bits and parity bits, which is obtained by encoding second data in a second encoding process, and to adjust an occupation rate of parity bits in the first data block that is closer to an occupation rate of parity bits in the second data block, in regard to first bit positions of the bit sequences generated using bits included in the first and second data blocks and performs multi-level modulation for transmission based on the generated bit sequences.
    • 一种发送装置发送数据的方法,包括控制比特序列的产生,以调整包含系统比特和奇偶校验比特在内的第一数据块中的系统比特的占有率,该第一数据块是通过在第一编码处理中对第一数据进行编码而获得的,以及 在第二数据块中的系统比特的占有率等于或更接近于包括通过在第二编码处理中对第二数据进行编码而获得的系统比特和奇偶校验比特的第二数据块的占有率,并且调整第一数据块中的奇偶校验比特的占有率 关于使用包括在第一和第二数据块中的位产生的比特序列的第一比特位置,更靠近第二数据块中的奇偶校验位的占有率,并且基于生成的比特执行用于发送的多级调制 序列。
    • 9. 发明授权
    • Method and apparatus for controlling transmitting, receiving, and re-transmission
    • 用于控制发送,接收和重传的方法和装置
    • US07685504B2
    • 2010-03-23
    • US10963811
    • 2004-10-14
    • Kazuhisa ObuchiTetsuya YanoShunji Miyazaki
    • Kazuhisa ObuchiTetsuya YanoShunji Miyazaki
    • H03M13/03
    • H04L1/0068H04L1/0075H04L1/08H04L1/1819H04L1/1845
    • A method and apparatus operable to execute an error correction decoding process, while controlling the increase in the amount of data that is stored in the receiving apparatus, is disclosed. Data is preferably transmitted to a receiving apparatus to execute the error correction decoding process using received data and re-transmitted data. Transmitting data is generated by executing the rate matching process to a first part of the error correction coded data and generating a second transmitting data. The second transmitting data includes at least the data not included in the first part by executing the rate matching process. Also included is a transmitting means for executing the transmission of the second transmitting data as the re-transmission after the transmission of the first transmitting data.
    • 公开了一种在控制存储在接收装置中的数据量的增加的同时执行纠错解码处理的方法和装置。 优选地,将数据发送到接收装置,以使用接收的数据和重新发送的数据来执行纠错解码处理。 通过对纠错编码数据的第一部分执行速率匹配处理并产生第二发送数据来生成发送数据。 第二发送数据至少包括通过执行速率匹配处理而不包括在第一部分中的数据。 还包括发送装置,用于在发送第一发送数据之后执行第二发送数据的发送作为再发送。