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1. 发明授权

US06831021B2 Plasma method and apparatus for processing a substrate 有权
标题翻译：用于处理衬底的等离子体方法和设备
公开(公告)号：US06831021B2
公开(公告)日：2004-12-14
申请号：US10461083
申请日：2003-06-12
申请人： Tal Cheng Chua , Philip Allan Kraus , John Holland
发明人： Tal Cheng Chua , Philip Allan Kraus , John Holland
IPC分类号： H01L21469
CPC分类号： H01L21/28202 , H01J37/321 , H01L21/3144 , H01L21/3185
摘要： Embodiments of the invention generally provide a method of forming a nitride gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via introduction of a nitrogen-containing processing gas into the processing chamber and the application of an ionizing energy to the processing gas, and pulsing the ionizing energy to maintain a mean temperature of electrons in the nitrogen-containing plasma of less than about 0.7 eV.
摘要翻译：本发明的实施例通常提供形成氮化物栅极电介质层的方法。该方法包括通过在处理室中引入含氮处理气体和向处理气体中施加电离能，并且使电离能脉冲以维持电子的平均温度，从而在处理室中产生含氮等离子体在含氮等离子体中小于约0.7eV。

2. 发明授权

US06660659B1 Plasma method and apparatus for processing a substrate 有权
标题翻译：用于处理衬底的等离子体方法和设备
公开(公告)号：US06660659B1
公开(公告)日：2003-12-09
申请号：US10170925
申请日：2002-06-12
申请人： Philip Allan Kraus , Thai Cheng Chua , John Holland , James P. Cruse
发明人： Philip Allan Kraus , Thai Cheng Chua , John Holland , James P. Cruse
IPC分类号： H01L2131
CPC分类号： H01L21/0234 , H01J37/321 , H01L21/02332 , H01L21/3144 , H01L21/3185
摘要： According to one aspect of the invention, a method is provided of processing a substrate, including locating the substrate in a processing chamber, creating a nitrogen plasma in the chamber, the plasma having an ion density of at least 1010 cm−3, and a potential of less than 20 V, and exposing a layer on the substrate to the plasma to incorporate nitrogen of the plasma into the layer.
摘要翻译：根据本发明的一个方面，提供了一种处理衬底的方法，包括将衬底定位在处理室中，在腔室中产生氮等离子体，等离子体具有至少10cm -1的离子密度， 3>，并且电位低于20V，并将衬底上的层暴露于等离子体以将等离子体的氮引入层中。

3. 发明申请

US20180138061A1 SELECTIVE ETCH RATE MONITOR 有权
公开(公告)号：US20180138061A1
公开(公告)日：2018-05-17
申请号：US15351437
申请日：2016-11-14
申请人： Philip Allan Kraus , Timothy J. Franklin
发明人： Philip Allan Kraus , Timothy J. Franklin
IPC分类号： H01L21/67 , H01L21/66 , G01H13/00
CPC分类号： H01L21/67253 , G01H13/00 , H01J37/00 , H01L21/67069 , H01L21/67155 , H01L22/14 , H01L22/26
摘要： Embodiments include a real time etch rate sensor and methods of for using a real time etch rate sensor. In an embodiment, the real time etch rate sensor includes a resonant system and a conductive housing. The resonant system may include a resonating body, a first electrode formed over a first surface of the resonating body, a second electrode formed over a second surface of the resonating body, and a sacrificial layer formed over the first electrode. In an embodiment, at least a portion of the first electrode is not covered by the sacrificial layer. In an embodiment, the conductive housing may secure the resonant system. Additionally, the conductive housing contacts the first electrode, and at least a portion of an interior edge of the conductive housing may be spaced away from the sacrificial layer.

4. 发明申请

US20090042354A1 INTEGRATED CIRCUIT FABRICATION PROCESS USING A COMPRESSION CAP LAYER IN FORMING A SILICIDE WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION 有权
标题翻译：集成电路制造工艺使用压缩层形成硅胶，具有最小的后激光退火猝死
公开(公告)号：US20090042354A1
公开(公告)日：2009-02-12
申请号：US11836326
申请日：2007-08-09
申请人： YI Ma , Philip Allan Kraus , Christopher Sean Olsen , Khaled Z. Ahmed , Abhilash J. Mayur
发明人： YI Ma , Philip Allan Kraus , Christopher Sean Olsen , Khaled Z. Ahmed , Abhilash J. Mayur
IPC分类号： H01L21/336
CPC分类号： B23K26/0738 , B23K26/082 , B23K26/0876 , H01L21/268 , H01L21/28518 , H01L21/76828 , H01L29/665
摘要： Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying compression cap layer, to prevent metal agglomeration at the silicon melting temperature. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing near the silicon melting temperature.
摘要翻译：通过在激光退火之前执行特定的硅化物形成工艺步骤，使激光后退火掺杂剂失活最小化。在源极 - 漏极区域和栅极电极上沉积贱金属层，随后沉积上覆的压缩覆盖层，以防止在硅熔融温度下的金属聚集。此后，进行快速热处理以充分加热衬底，以在源极 - 漏极区域和栅电极的顶表面处形成金属硅化物接触。该方法还包括去除剩余的含金属层，然后在靠近硅熔化温度的激光退火之前，在衬底上沉积光吸收层。

5. 发明申请

US20080076268A1 FLUORINE PLASMA TREATMENT OF HIGH-K GATE STACK FOR DEFECT PASSIVATION 有权
标题翻译：用于缺陷钝化的高K栅格堆的氟等离子体处理
公开(公告)号：US20080076268A1
公开(公告)日：2008-03-27
申请号：US11861578
申请日：2007-09-26
申请人： Philip Allan Kraus , Christopher Olsen , Khaled Z. Ahmed
发明人： Philip Allan Kraus , Christopher Olsen , Khaled Z. Ahmed
IPC分类号： H01L21/31
CPC分类号： H01L21/3115 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/518
摘要： Embodiments of the present invention generally provide a method for forming a dielectric material with reduced bonding defects on a substrate. In one embodiment, the method comprises forming a dielectric layer having a desired thickness on a surface of a substrate, exposing the substrate to a low energy plasma comprising a fluorine source gas to form a fluorinated dielectric layer on the substrate without etching the dielectric layer, and forming a gate electrode on the substrate. In certain embodiments, the fluorine source gas is a carbon free gas. In certain embodiments, the method further comprises co-flowing a gas selected from the group consisting of argon, helium, N2, O2, and combinations thereof with the fluorine source gas.
摘要翻译：本发明的实施方案通常提供一种在基片上形成具有降低的结合缺陷的电介质材料的方法。在一个实施例中，该方法包括在衬底的表面上形成具有所需厚度的电介质层，将衬底暴露于包含氟源气体的低能量等离子体，以在衬底上形成氟化电介质层，而不蚀刻介电层，以及在所述衬底上形成栅电极。在某些实施方案中，氟源气体是无碳气体。在某些实施方案中，该方法还包括将选自氩，氦，N 2，O 2，及其组合的气体与氟源共流加油站。

6. 发明授权

US07888217B2 Method for fabricating a gate dielectric of a field effect transistor 有权
标题翻译：用于制造场效应晶体管的栅极电介质的方法
公开(公告)号：US07888217B2
公开(公告)日：2011-02-15
申请号：US11255857
申请日：2005-10-20
申请人： Thai Cheng Chua , Cory Czarnik , Christopher Sean Olsen , Khaled Z. Ahmed , Philip Allan Kraus
发明人： Thai Cheng Chua , Cory Czarnik , Christopher Sean Olsen , Khaled Z. Ahmed , Philip Allan Kraus
IPC分类号： H01L21/336
CPC分类号： H01L21/31662 , H01L21/0214 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02252 , H01L21/02255 , H01L21/02271 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L21/3185 , H01L21/823857 , H01L29/518 , Y10S438/908
摘要： A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, oxidizing the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. Optionally, the gate dielectric layer may be nitridized prior to oxidizing the gate dielectric layer. In one embodiment, at least portions of the method are performed using processing reactors arranged on a cluster tool.
摘要翻译：本文公开了一种用于制造场效应晶体管的栅极电介质的方法。在一个实施例中，该方法包括以下步骤：去除自然氧化物层，形成氧化物层，在氧化物层上形成栅极电介质层，氧化栅极电介质层，以及退火层和下面的热氧化物/硅界面。任选地，氧化物层可以在形成栅极电介质层之前被氮化。可选地，栅极电介质层可以在氧化栅极电介质层之前被氮化。在一个实施例中，使用布置在群集工具上的处理反应器来执行该方法的至少一部分。

7. 发明授权

US07737036B2 Integrated circuit fabrication process with minimal post-laser annealing dopant deactivation 失效
标题翻译：集成电路制造工艺，具有最小的激光后退火掺杂剂钝化
公开(公告)号：US07737036B2
公开(公告)日：2010-06-15
申请号：US11836267
申请日：2007-08-09
申请人： Yi Ma , Philip Allan Kraus , Christopher Sean Olsen , Khaled Z. Ahmed , Abhilash J. Mayur
发明人： Yi Ma , Philip Allan Kraus , Christopher Sean Olsen , Khaled Z. Ahmed , Abhilash J. Mayur
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , B23K26/0006 , B23K26/0608 , B23K26/0622 , B23K26/064 , B23K26/0648 , B23K26/0665 , B23K26/0738 , B23K26/0876 , B23K26/352 , B23K2101/42 , B23K2103/56 , H01L21/268 , H01L21/28518
摘要： Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing.
摘要翻译：通过在激光退火之前执行某些低温工艺步骤，使激光后退火掺杂剂失活最小化。

8. 发明授权

US07727828B2 Method for fabricating a gate dielectric of a field effect transistor 有权
标题翻译：用于制造场效应晶体管的栅极电介质的方法
公开(公告)号：US07727828B2
公开(公告)日：2010-06-01
申请号：US11381960
申请日：2006-05-05
申请人： Thai Cheng Chua , Cory Czarnik , Andreas G. Hegedus , Christopher Sean Olsen , Khaled Z. Ahmed , Philip Allan Kraus
发明人： Thai Cheng Chua , Cory Czarnik , Andreas G. Hegedus , Christopher Sean Olsen , Khaled Z. Ahmed , Philip Allan Kraus
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/3144 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02252 , H01L21/02255 , H01L21/02271 , H01L21/02274 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/31662 , H01L21/3185 , H01L21/823857 , H01L29/518
摘要： A method for fabricating a gate dielectric of a field effect transistor is provided. In one embodiment, the method includes removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, forming an oxide layer over the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. In one embodiment, the oxide layer on the substrate is formed by depositing the oxide layer, and the oxide layer on the gate dielectric layer is formed by oxidizing at least a portion of the gate dielectric layer using an oxygen-containing plasma. In another embodiment, the oxide layer on the gate dielectric layer is formed by forming a thermal oxide layer, i.e., depositing the oxide layer on the gate dielectric layer.
摘要翻译：提供了一种用于制造场效应晶体管的栅极电介质的方法。在一个实施例中，该方法包括去除自然氧化物层，形成氧化物层，在氧化物层上形成栅极电介质层，在栅极电介质层上形成氧化物层，以及退火层和下面的热氧化物/硅界面。任选地，氧化物层可以在形成栅极电介质层之前被氮化。在一个实施例中，通过沉积氧化物层形成衬底上的氧化物层，并且通过使用含氧等离子体氧化至少一部分栅极电介质层来形成栅极电介质层上的氧化物层。在另一个实施例中，栅极电介质层上的氧化物层通过形成热氧化物层，即将氧化物层沉积在栅极电介质层上而形成。

9. 发明申请

US20090042353A1 INTEGRATED CIRCUIT FABRICATION PROCESS FOR A HIGH MELTING TEMPERATURE SILICIDE WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION 审中-公开
标题翻译：用于具有最小激光退火猝死活性的高熔点温度硅胶的集成电路制造工艺
公开(公告)号：US20090042353A1
公开(公告)日：2009-02-12
申请号：US11836299
申请日：2007-08-09
申请人： Yi Ma , Philip Allan Kraus , Christopher Sean Olsen , Khaled Z. Ahmed , Abhilash J. Mayur
发明人： Yi Ma , Philip Allan Kraus , Christopher Sean Olsen , Khaled Z. Ahmed , Abhilash J. Mayur
IPC分类号： H01L21/331
CPC分类号： B23K26/0738 , B23K26/082 , B23K26/0876 , H01L21/268 , H01L29/665
摘要： Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer of nickel is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying layer of a metal having a higher melting temperature than nickel. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing.
摘要翻译：通过在激光退火之前执行特定的硅化物形成工艺步骤，使激光后退火掺杂剂失活最小化。在源 - 漏区和栅电极上沉积镍的贱金属层，然后沉积具有比镍更高的熔融温度的金属的上覆层。此后，进行快速热处理以充分加热衬底，以在源极 - 漏极区域和栅电极的顶表面处形成金属硅化物接触。该方法还包括去除剩余的含金属层，然后在激光退火之前在衬底上沉积光吸收层。

10. 发明授权

US07659187B2 Method of forming PN junctions including a post-ion implant dynamic surface anneal process with minimum interface trap density at the gate insulator-silicon interface 失效
标题翻译：在栅极绝缘体 - 硅界面处形成具有最小界面陷阱密度的离子后植入物动态表面退火工艺的PN结的方法
公开(公告)号：US07659187B2
公开(公告)日：2010-02-09
申请号：US11735947
申请日：2007-04-16
申请人： Philip Allan Kraus , Vijay Parihar
发明人： Philip Allan Kraus , Vijay Parihar
IPC分类号： H01L21/425
CPC分类号： H01L21/268 , H01L21/26513 , H01L21/823418 , H01L29/66575
摘要： A method of forming transistors on a wafer includes forming gates over gate insulators on a surface of the wafer and ion implanting dopant impurity atoms into the wafer to form source and drain regions aligned on opposite sides of each gate. The wafer is then annealed by pre-heating the bulk of the wafer to an elevated temperature over 350 degrees C. but below a temperature at which the dopant atoms tend to cluster. Meanwhile, an intense line beam is produced having a narrow dimension along a fast axis from an array of coherent CW lasers of a selected wavelength. This line beam is scanned across the surface of the heated wafer along the direction of the fast axis, so as to heat, up to a peak surface temperature near a melting temperature of the wafer, a moving localized region on the surface of the wafer having (a) a width corresponding to the narrow beam width and (b) an extremely shallow below-surface depth. During the scanning step, the surface state density at the interface between the semiconductor material and the gate insulator is minimized by continuing to maintain the temperature of the bulk of the wafer outside of the moving localized region at said elevated temperature, while maintaining the rate at which the line beam is scanned along the fast axis at a rate in excess of 300 mm/sec.
摘要翻译：在晶片上形成晶体管的方法包括在晶片的表面上的栅极绝缘体上形成栅极，并将离子注入掺杂杂质原子放入晶片中以形成在每个栅极的相对侧对准的源区和漏区。然后通过将晶片的大部分预热至350℃以上的高温但低于掺杂剂原子倾向于聚集的温度来退火晶片。同时，产生沿着来自所选波长的相干CW激光器阵列的快轴具有窄尺寸的强线束。该线束沿加热晶片的表面沿着快轴的方向扫描，以加热直到晶片的熔化温度附近的峰值表面温度，晶片表面上的移动局部区域具有（a）对应于窄梁宽度的宽度和（b）非常浅的下表面深度。在扫描步骤期间，通过在所述升高的温度下继续将晶片的主体的温度保持在移动的局部区域的外部，同时将速率保持在该范围内，使半导体材料和栅极绝缘体之间的界面处的表面状态密度最小化其中线束以快速轴线以超过300mm / sec的速率扫描。

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