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1. 发明授权

US06242349B1 Method of forming copper/copper alloy interconnection with reduced electromigration 有权
标题翻译：形成铜/铜合金互连的方法，减少电迁移
公开(公告)号：US06242349B1
公开(公告)日：2001-06-05
申请号：US09207680
申请日：1998-12-09
申请人： Takeshi Nogami , Sergey Lopatin , Young-Chang Joo
发明人： Takeshi Nogami , Sergey Lopatin , Young-Chang Joo
IPC分类号： H01L2144
CPC分类号： H01L21/76874 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H05K1/0306 , H05K3/388
摘要： The electromigration of a Cu or Cu alloy interconnection member is reduced by annealing the seed layer before electroplating or electroless plating the Cu or Cu alloy interconnection member on the seed layer. Embodiments include depositing a Cu or Cu alloy seed layer, annealing at about 100° C. to about 400° C. to increase the grain size of the seed layer and impart a (111)-dominant crystallographic option before plating the Cu or Cu alloy interconnect member thereon the seed layer
摘要翻译：通过在种子层上电镀或无电镀Cu或Cu合金互连构件之前退火种子层，可以减少Cu或Cu合金互连构件的电迁移。实施方案包括沉积Cu或Cu合金种子层，在约100℃至约400℃退火以增加种子层的晶粒尺寸并在镀覆Cu或Cu合金之前赋予（111） - 显性晶体选择互连部件上的籽晶层

2. 发明授权

US06563222B1 Method and apparatus for reducing electromigration in semiconductor interconnect lines 有权
标题翻译：用于减少半导体互连线路中的电迁移的方法和装置
公开(公告)号：US06563222B1
公开(公告)日：2003-05-13
申请号：US09999703
申请日：2001-10-24
申请人： Takeshi Nogami , Sergey Lopatin
发明人： Takeshi Nogami , Sergey Lopatin
IPC分类号： H01L2348
CPC分类号： H01L21/76877 , H01L21/76886 , H01L2924/0002 , H01L2924/00
摘要： A method for making a semiconductor chip includes disposing copper interconnects adjacent via channels and then doping only the portions of the interconnects that lie directly beneath the via channels. Then, the via channels are filled with electrically conductive material. The impurities with which the interconnects are locally doped reduce unwanted electromigration of copper atoms at the interconnect-via interfaces, while not unduly increasing line resistance in the interconnects.
摘要翻译：一种用于制造半导体芯片的方法包括：经由沟道邻近布置铜互连，然后仅掺杂直接位于通孔通道下方的互连部分。然后，通孔通道填充有导电材料。局部掺杂互连的杂质减少了互连通孔界面处铜原子的不必要的电迁移，同时不会过度增加互连中的线电阻。

3. 发明授权

US6103624A Method of improving Cu damascene interconnect reliability by laser anneal before barrier polish 有权
标题翻译：通过激光退火改善铜镶嵌互连可靠性的方法
公开(公告)号：US6103624A
公开(公告)日：2000-08-15
申请号：US293559
申请日：1999-04-15
申请人： Takeshi Nogami , Dirk D. Brown , Sergey Lopatin
发明人： Takeshi Nogami , Dirk D. Brown , Sergey Lopatin
IPC分类号： H01L21/768 , H01L23/532 , H01L21/441 , H01L21/428 , H01L21/445 , H01L21/447
CPC分类号： H01L23/53238 , H01L21/76838 , H01L21/76877 , H01L2924/0002
摘要： Semiconductor devices with copper interconnects wherein a barrier metal layer is applied over the surface of a dielectric layer with a plurality of trenches. The barrier metal layer lines the trenches. A copper layer is placed over the barrier metal layer and fills the trenches. The part of the copper layer that is not inside the trenches is polished away, making sure that the barrier metal layer is not polished away. The copper layer is laser annealed to increase the grain size, remove seams, and provide a better interface bond between the barrier metal layer and the copper layer. The barrier metal layer protects the dielectric layer during the annealing process. The part of the barrier metal layer that is not in the trenches is removed by polishing.
摘要翻译：具有铜互连的半导体器件，其中阻挡金属层被施加在具有多个沟槽的电介质层的表面上。阻挡层金属层对沟槽进行排列。将铜层放置在阻挡金属层上方并填充沟槽。不在沟槽内部的铜层的部分被抛光，确保阻挡金属层不被抛光。铜层被激光退火以增加晶粒尺寸，去除接缝，并且在阻挡金属层和铜层之间提供更好的界面结合。阻挡金属层在退火过程中保护介电层。通过抛光除去不在沟槽中的阻挡金属层的一部分。

4. 发明授权

US06281587B1 Multi-layered coaxial interconnect structure 有权
标题翻译：多层同轴互连结构
公开(公告)号：US06281587B1
公开(公告)日：2001-08-28
申请号：US09522148
申请日：2000-03-09
申请人： Takeshi Nogami , Sergey Lopatin , Shekhar Pramanick
发明人： Takeshi Nogami , Sergey Lopatin , Shekhar Pramanick
IPC分类号： H01L2348
CPC分类号： H01L21/76885 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a multi-layered interconnect structure is provided. A first conductive pattern is formed over an insulation layer. A first dielectric material is deposited over the first conductive pattern, and plugs are formed in the first dielectric material. A second conductive pattern is formed over the first dielectric material and plugs so as to form the multi-layered interconnect structure in part. Then, the first dielectric material is stripped away to leave the multi-layered interconnect structure exposed to air. A thin layer of second dielectric material is deposited so as to coat at least a portion of the interconnect structure. Next, a thin layer of metal is deposited so as to coat the at least a portion of the interconnect structure coated with the thin layer of second dielectric material. A third dielectric material is deposited over the interconnect structure to replace the stripped away first dielectric material.
摘要翻译：提供一种形成多层互连结构的方法。在绝缘层上形成第一导电图案。在第一导电图案上沉积第一介电材料，并且在第一介电材料中形成插塞。在第一电介质材料上形成第二导电图案并且插塞以部分地形成多层互连结构。然后，将第一介电材料剥离掉，使多层互连结构暴露于空气。沉积薄层的第二介电材料以涂覆至少一部分互连结构。接下来，沉积薄层金属，以涂覆涂覆有第二介电材料的薄层的互连结构的至少一部分。第三介电材料沉积在互连结构上以代替剥离的第一介电材料。

5. 发明授权

US6060383A Method for making multilayered coaxial interconnect structure 有权
标题翻译：制造多层同轴互连结构的方法
公开(公告)号：US6060383A
公开(公告)日：2000-05-09
申请号：US131919
申请日：1998-08-10
申请人： Takeshi Nogami , Sergey Lopatin , Shekhar Pramanick
发明人： Takeshi Nogami , Sergey Lopatin , Shekhar Pramanick
IPC分类号： H01L21/768 , H01L21/465 , H01L21/469 , H01L21/47 , H01L21/471 , H01L21/475 , H01L21/4763
CPC分类号： H01L21/76885 , H01L23/5222 , H01L2924/0002
摘要： A method of forming a multi-layered interconnect structure is provided. A first conductive pattern is formed over an insulation layer. A first dielectric material is deposited over the first conductive pattern, and plugs are formed in the first dielectric material. A second conductive pattern is formed over the first dielectric material and plugs so as to form the multi-layered interconnect structure in part. Then, the first dielectric material is stripped away to leave the multi-layered interconnect structure exposed to air. A thin layer of second dielectric material is deposited so as to coat at least a portion of the interconnect structure. Next, a thin layer of metal is deposited so as to coat the at least a portion of the interconnect structure coated with the thin layer of second dielectric material. A third dielectric material is deposited over the interconnect structure to replace the stripped away first dielectric material.
摘要翻译：提供一种形成多层互连结构的方法。在绝缘层上形成第一导电图案。在第一导电图案上沉积第一介电材料，并且在第一介电材料中形成插塞。在第一电介质材料上形成第二导电图案并且插塞以部分地形成多层互连结构。然后，将第一介电材料剥离掉，使多层互连结构暴露于空气。沉积薄层的第二介电材料以涂覆至少一部分互连结构。接下来，沉积薄层金属，以涂覆涂覆有第二介电材料的薄层的互连结构的至少一部分。第三介电材料沉积在互连结构上以代替剥离的第一介电材料。

6. 发明授权

US6096648A Copper/low dielectric interconnect formation with reduced electromigration 有权
标题翻译：具有减少电迁移的铜/低介电互连形成
公开(公告)号：US6096648A
公开(公告)日：2000-08-01
申请号：US237584
申请日：1999-01-26
申请人： Sergey Lopatin , Takeshi Nogami , Robin W. Cheung , Christy Mei-Chu Woo , Guarionex Morales
发明人： Sergey Lopatin , Takeshi Nogami , Robin W. Cheung , Christy Mei-Chu Woo , Guarionex Morales
IPC分类号： H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76886 , H01L21/76819 , H01L21/76835 , H01L21/76837 , H01L21/76885
摘要： A method of metallizing a semiconductor chip with copper including an inlaid low dielectric constant layer. The method includes the step of depositing a barrier layer on the surface of the semiconductor chip. Next, a copper seed layer is deposited on the barrier layer, and then the copper seed layer is annealed. Microlithography is then performed on the semiconductor chip to form a plurality of wiring line paths with a patterned photoresist layer. After the wiring line paths are formed a copper conductive layer is electroplated to the surface of the semiconductor chip. Next, the patterned photoresist layer is stripped off of the surface of the semiconductor chip. In addition, portions of the barrier layer and the copper seed layer that were covered by the patterned photoresist layer are also removed. A low dielectric constant layer is then deposited on the semiconductor chip to fill the gaps between the newly created copper conductive lines.
摘要翻译：一种用包括嵌入的低介电常数层的铜对半导体芯片进行金属化的方法。该方法包括在半导体芯片的表面上沉积阻挡层的步骤。接下来，在阻挡层上沉积铜籽晶层，然后对铜籽晶层进行退火。然后在半导体芯片上进行微光刻，以形成具有图案化光致抗蚀剂层的多条布线路径。在形成布线路径之后，将铜导电层电镀到半导体芯片的表面。接下来，将图案化的光致抗蚀剂层剥离出半导体芯片的表面。此外，也去除了被图案化光致抗蚀剂层覆盖的阻挡层和铜籽晶层的部分。然后在半导体芯片上沉积低介电常数层以填充新生成的铜导线之间的间隙。

7. 发明授权

US06346470B1 Method for reducing electromigration in semiconductor interconnect lines 有权
标题翻译：减少半导体互连线路中电迁移的方法
公开(公告)号：US06346470B1
公开(公告)日：2002-02-12
申请号：US09294454
申请日：1999-04-19
申请人： Takeshi Nogami , Sergey Lopatin
发明人： Takeshi Nogami , Sergey Lopatin
IPC分类号： H01L214763
CPC分类号： H01L21/76877 , H01L21/76886 , H01L2924/0002 , H01L2924/00
摘要： A method for making a semiconductor chip includes disposing copper interconnects adjacent via channels and then doping only the portions of the interconnects that lie directly beneath the via channels. Then, the via channels are filled with electrically conductive material. The impurities with which the interconnects are locally doped reduce unwanted electromigration of copper atoms at the interconnect-via interfaces, while not unduly increasing line resistance in the interconnects.
摘要翻译：一种用于制造半导体芯片的方法包括：经由沟道邻近布置铜互连，然后仅掺杂直接位于通孔通道下方的互连部分。然后，通孔通道填充有导电材料。局部掺杂互连的杂质减少了互连通孔界面处铜原子的不必要的电迁移，同时不会过度增加互连中的线电阻。

8. 发明授权

US06015747A Method of metal/polysilicon gate formation in a field effect transistor 失效
标题翻译：场效应晶体管中金属/多晶硅栅极形成的方法
公开(公告)号：US06015747A
公开(公告)日：2000-01-18
申请号：US206799
申请日：1998-12-07
申请人： Sergey Lopatin , Takeshi Nogami , Shekhar Pramanik
发明人： Sergey Lopatin , Takeshi Nogami , Shekhar Pramanik
IPC分类号： H01L21/28 , H01L21/336 , H01L21/335
CPC分类号： H01L29/6659 , H01L21/28061 , H01L29/41783 , H01L29/665 , H01L29/66545
摘要： A method for manufacturing a field effect transistor (100) includes forming source and drain regions (110, 112) in a semiconductor substrate (102) and forming a polysilicon gate (104) on a surface (106) of the semiconductor substrate adjacent to the source and drain regions. A masking layer (136) is formed, covering substantially all the semiconductor substrate. Portions of the masking layer are then selectively removed to expose at least selected portions of the polysilicon gate. Selected portions of the polysilicon gate are partially etched. By selective electroless metal deposition, a metal layer (146) is formed on the etched selected portions of the polysilicon gate. In an alternative embodiment, the masking layer is removed before selective deposition of the electroless metal, so that electroless metal is simultaneously deposited on the polysilicon gate and the source region and the drain region.
摘要翻译：一种用于制造场效应晶体管（100）的方法包括在半导体衬底（102）中形成源区和漏区（110,112），并在与半导体衬底相邻的半导体衬底的表面（106）上形成多晶硅栅极（104）源极和漏极区域。形成掩蔽层（136），覆盖基本上所有的半导体衬底。然后选择性地去除掩模层的部分以暴露多晶硅栅极的至少选定部分。部分蚀刻多晶硅栅极的选定部分。通过选择性无电金属沉积，在多晶硅栅极的蚀刻的选定部分上形成金属层（146）。在替代实施例中，在选择性沉积无电金属之前去除掩模层，使得化学金属同时沉积在多晶硅栅极和源极区域和漏极区域上。

9. 发明授权

US08969197B2 Copper interconnect structure and its formation 有权
标题翻译：铜互连结构及其形成
公开(公告)号：US08969197B2
公开(公告)日：2015-03-03
申请号：US13475526
申请日：2012-05-18
申请人： Daniel C. Edelstein , Takeshi Nogami , Christopher Parks , Tsong-Lin Tai
发明人： Daniel C. Edelstein , Takeshi Nogami , Christopher Parks , Tsong-Lin Tai
IPC分类号： H01L21/44
CPC分类号： H01L23/53238 , H01L21/76849 , H01L21/76867 , H01L21/76883 , H01L23/522 , H01L23/53209 , H01L23/5329 , H01L23/53295 , H01L24/76 , H01L24/82 , H01L2924/0002 , H01L2924/00
摘要： A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.
摘要翻译：具有改进的电迁移阻力的结构及其制造方法。具有改进的电迁移电阻的结构包括具有双层盖和介电覆盖层的体互连。双层帽包括底部金属部分和顶部金属氧化物部分。优选地，金属氧化物部分是MnO或MnSiO，金属部分是Mn或CuMn。通过用杂质（在优选实施例中为Mn）掺杂互连，然后在互连的顶部处产生晶格缺陷来产生该结构。这些缺陷驱使增加的杂质向互连顶表面迁移。当形成电介质盖层时，一部分与分离的杂质反应，从而在互连上形成双层盖。 Cu表面的晶格缺陷可以通过等离子体处理，离子注入，压缩薄膜或其他方式产生。

10. 发明授权

US08841212B2 Method of making a copper interconnect having a barrier liner of multiple metal layers 有权
标题翻译：制造具有多个金属层的阻挡衬里的铜互连的方法
公开(公告)号：US08841212B2
公开(公告)日：2014-09-23
申请号：US13609668
申请日：2012-09-11
申请人： Takeshi Nogami , Thomas M. Shaw , Andrew H. Simon , Jean E. Wynne , Chih-Chao Yang
发明人： Takeshi Nogami , Thomas M. Shaw , Andrew H. Simon , Jean E. Wynne , Chih-Chao Yang
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53238 , H01L21/76844 , H01L21/76846 , H01L2924/0002 , H01L2924/00
摘要： A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.
摘要翻译：一种方法图形为多级集成电路结构的低K绝缘体层中的至少一个开口，使得铜导体在开口的底部露出。该方法然后在第一室中用第一钽氮化物层排列开口的侧壁和底部，并在第一室中的第一氮化钽层上形成钽层。接下来，在第一室中进行对开口的溅射蚀刻，以使开口底部的导体露出。在第一室中再次在导体，钽层和第一氮化钽层上形成第二钽氮化物层。在形成第二钽氮化物层之后，本文的方法在第二不同室中在第二氮化钽层上形成包含铂族金属的闪蒸层。

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