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    • 5. 发明授权
    • IC memory cells with reduced alpha particle influence
    • 具有降低的α粒子影响的IC记忆体
    • US4706107A
    • 1987-11-10
    • US830919
    • 1986-02-20
    • Kazuo TeradaSusumu KurosawaShunichi Suzuki
    • Kazuo TeradaSusumu KurosawaShunichi Suzuki
    • G11C11/404G11C11/4074H01L27/092H01L27/108H01L29/78
    • H01L29/7841G11C11/404G11C11/4074H01L27/092H01L27/108
    • A semiconductor memory device has a semiconductor substrate with a first semiconductor region of one conductivity type in the substrate. A second semiconductor region of the opposite conductivity type is formed in the first semiconductor region. A third semiconductor region of the opposite conductivity type is arranged to be in contact with the first semiconductor region. A fourth semiconductor region of the one conductivity type is formed in the third semiconductor region. A fifth semiconductor region of the one conductivity type, within the semiconductor substrate, has a concentration which is higher than the impurity concentration of the first semiconductor region and is provided under the third semiconductor region. A continuous gate electrode is provided via a gate insulating layer formed on the surface of the first semiconductor region and on the surface of the third semiconductor region. The first, second and third semiconductor regions and the gate electrode form a first insulated-gate field effect transistor. The second, third and fourth semiconductor regions and the gate electrode serving as a second insulated-gate field effect transistor.
    • 半导体存储器件具有在衬底中具有一种导电类型的第一半导体区域的半导体衬底。 在第一半导体区域中形成相反导电类型的第二半导体区域。 相反导电类型的第三半导体区域布置成与第一半导体区域接触。 在第三半导体区域中形成一种导电类型的第四半导体区域。 半导体衬底内的一种导电类型的第五半导体区域具有比第一半导体区域的杂质浓度高的浓度,并且设置在第三半导体区域的下方。 通过形成在第一半导体区域的表面上和第三半导体区域的表面上的栅极绝缘层提供连续的栅电极。 第一,第二和第三半导体区域和栅电极形成第一绝缘栅场效应晶体管。 第二,第三和第四半导体区域和用作第二绝缘栅场效应晶体管的栅电极。