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1. 发明授权

US06026036A Synchronous semiconductor memory device having set up time of external address signal reduced 有权
标题翻译：具有缩短外部地址信号设定时间的同步半导体存储器件
公开(公告)号：US06026036A
公开(公告)日：2000-02-15
申请号：US212308
申请日：1998-12-16
申请人： Takashi Sekiya , Tomohisa Wada , Kunihiko Kozaru
发明人： Takashi Sekiya , Tomohisa Wada , Kunihiko Kozaru
IPC分类号： G11C11/413 , G11C7/10 , G11C8/06 , G11C8/10 , G11C11/408 , G11C29/04 , G11C7/00 , G11C8/00
CPC分类号： G11C7/225 , G11C7/1072 , G11C8/06 , G11C8/10
摘要： In a synchronous semiconductor memory device, a predecoder is provided between a former stage address input register formed of first latch circuits and a latter stage address input register formed of second latch circuits. The first and second latch circuits operate in response to first and second internal clock signals complementary to each other. A predecode signal can be latched by the second latch circuit even when the generation of the predecode signal is not in time for the rise of the second internal dock signal due to delay of the input of an external address signal. Accordingly, the set up time for the external address signal can be reduced.
摘要翻译：在同步半导体存储器件中，在由第一锁存电路形成的前级地址输入寄存器和由第二锁存电路形成的后级地址输入寄存器之间提供预解码器。第一和第二锁存电路响应彼此互补的第一和第二内部时钟信号而工作。即使当由于外部地址信号的输入的延迟而导致第二内部停靠信号的上升，预编码信号的生成不及时时，也可以由第二锁存电路锁存预解码信号。因此，可以减少外部地址信号的建立时间。

2. 发明授权

US5929539A Semiconductor memory device adaptable to external power supplies of different voltage levels 失效
标题翻译：半导体存储器件适用于不同电压等级的外部电源
公开(公告)号：US5929539A
公开(公告)日：1999-07-27
申请号：US897614
申请日：1997-07-21
申请人： Kunihiko Kozaru , Tomohisa Wada
发明人： Kunihiko Kozaru , Tomohisa Wada
IPC分类号： G11C11/413 , G05F1/46 , G11C5/14 , G11C8/08 , G11C11/407 , H02J1/10
CPC分类号： G11C5/14 , G05F1/465 , G11C5/147 , G11C8/08 , Y10T307/675 , Y10T307/696 , Y10T307/724 , Y10T307/858
摘要： A semiconductor memory device includes a plurality of external power supply pads P1 to P3. Connection between external power supply pads P1 to P3 and an external power supply is determined in accordance with the voltage of the external power supply to be used, and the connection is switched by bonding. External power supply of a high voltage level is connected to an external power supply pad P2 which is connected to VDC1 and VDC2. A circuit including memory cells operates using the voltage applied from VDC1 or external power supply pad P3, while a group of word line drivers operates using the voltage applied from VDC2 or external power supply pad P1. VDC1 down converts the external power supply voltage, and VDC2 down converts it in accordance with the level of the voltage of the external power supply voltage, and generates internal power supply voltages, respectively. Accordingly, a semiconductor memory device which operates adapted to different external power supplies can be obtained.
摘要翻译：半导体存储器件包括多个外部电源焊盘P1至P3。根据要使用的外部电源的电压来确定外部电源焊盘P1至P3与外部电源之间的连接，并且通过焊接切换连接。高电压电平的外部电源连接到连接到VDC1和VDC2的外部电源焊盘P2。包括存储单元的电路使用从VDC1或外部电源焊盘P3施加的电压进行工作，而一组字线驱动器使用从VDC2或外部电源焊盘P1施加的电压进行操作。 VDC1下降转换外部电源电压，VDC2根据外部电源电压的电平降低转换，分别产生内部电源电压。因此，可以获得适用于不同外部电源的半导体存储器件。

3. 发明授权

US5841961A Semiconductor memory device including a tag memory 失效
标题翻译：包括标签存储器的半导体存储器件
公开(公告)号：US5841961A
公开(公告)日：1998-11-24
申请号：US487214
申请日：1995-06-07
申请人： Kunihiko Kozaru , Tomohisa Wada , Hirotoshi Sato
发明人： Kunihiko Kozaru , Tomohisa Wada , Hirotoshi Sato
IPC分类号： G06F12/08 , G11C29/00 , G11C29/04 , G06F11/00 , G06F11/16
CPC分类号： G11C29/80 , G11C29/808 , G11C29/848
摘要： In repairing a defective memory cell of a data memory placed in a data memory region, a repairing circuit which employs a repairing method causing some access penalty but having high repairing efficiency is located in a redundant row region and a redundant column region in the data memory region. On the other hand, in repairing a defective memory cell of a tag memory placed in a tag memory region, a repairing circuit which employs a repairing method having low repairing efficiency but causing little access penalty is located in a redundant column region in the tag memory region. Accordingly, optimal repair of a defective memory cell can be achieved according to respective functions of the tag memory and the data memory.
摘要翻译：在修复放置在数据存储器区域中的数据存储器的有缺陷的存储单元的情况下，采用修复方法引起一些访问损失但具有高修复效率的修复电路位于数据存储器中的冗余行区域和冗余列区域中地区。另一方面，在修复放置在标签存储区域中的标签存储器的有缺陷的存储单元的情况下，使用维修效率低但导致小的访问损失的修复方法的修复电路位于标签存储器的冗余列区域中地区。因此，可以根据标签存储器和数据存储器的各自的功能来实现对缺陷存储单元的最佳修复。

4. 发明授权

US5687111A Static type semiconductor memory device capable of operating at a low voltage and reducing a memory cell area 失效
标题翻译：静态型半导体存储器件能够以低电压工作并减少存储单元面积
公开(公告)号：US5687111A
公开(公告)日：1997-11-11
申请号：US609313
申请日：1996-03-01
申请人： Tomohisa Wada , Kunihiko Kozaru , Toru Shiomi
发明人： Tomohisa Wada , Kunihiko Kozaru , Toru Shiomi
IPC分类号： G11C11/411 , G11C11/41 , G11C11/412 , G11C14/00 , H01L21/8244 , H01L27/11 , G11C11/00 , H01L27/02
CPC分类号： H01L27/1112 , G11C11/412 , H01L27/11 , H01L27/1104 , H01L27/1108 , Y10S257/903
摘要： A pair of driving bipolar transistors of a lateral type T1 and T2 have emitters coupled to a ground potential, collectors connected to a pair of highly resistive elements R1 and R2. Highly resistive elements R1 and R2 have respective other ends coupled to power supply potential V.sub.CC, and bases and collectors of transistors T1 and T2 are cross-connected to each other, thereby forming a flipflop circuit. Access MOS transistors Q3 and Q4 having a gate potential controlled by word line WL are each connected to form a conduction path between one of storage nodes A and B and one of the pair of bit lines BL and /BL.
摘要翻译：横向型T1和T2的一对驱动双极晶体管具有耦合到接地电位的发射极，与一对高电阻元件R1和R2连接的集电极。高电阻元件R1和R2具有耦合到电源电位VCC的相应的另一端，并且晶体管T1和T2的基极和集电极彼此交叉连接，从而形成触发电路。具有由字线WL控制的栅极电位的接入MOS晶体管Q3和Q4分别被连接以形成存储节点A和B之一与一对位线BL和/ BL中的一个之间的导通路径。

5. 发明授权

US07902481B2 Method of manufacturing sealed electronic component and sealed electronic component 有权
标题翻译：密封电子元件和密封电子元件的制造方法
公开(公告)号：US07902481B2
公开(公告)日：2011-03-08
申请号：US11547323
申请日：2005-03-30
申请人： Keisuke Kigawa , Haruyuki Hiratsuka , Tomohisa Wada
发明人： Keisuke Kigawa , Haruyuki Hiratsuka , Tomohisa Wada
IPC分类号： H01L21/50 , B23K26/20
CPC分类号： H03H9/1021 , H01L21/50 , H03H3/02
摘要： A method of manufacturing a sealed electronic component, which can seal a housing in a high-vacuum state while preventing enclosure of a gas within the housing, as well as achieving the improvement in manufacturing efficiency. According to the method, after forming an unwelded section by a primary welding process step, including a first beam irradiation process step and a second beam irradiation process step, annealing treatment is performed in an annealing process step by irradiating an electron beam to a predetermined portion on a locus of the electron beam formed in the first beam irradiation process step. The locus may be on a housing or a lid.
摘要翻译：一种制造密封电子部件的方法，其可以在高真空状态下密封壳体，同时防止气体在壳体内的封闭，以及实现制造效率的提高。根据该方法，在通过一次焊接工艺步骤形成未焊接部分之后，包括第一光束照射处理步骤和第二光束照射处理步骤，在退火处理步骤中通过将电子束照射到预定部分在第一光束照射处理步骤中形成的电子束的轨迹上。轨迹可以在壳体或盖子上。

6. 发明授权

US06327188B1 Synchronous random access memory 有权
标题翻译：同步随机存取存储器
公开(公告)号：US06327188B1
公开(公告)日：2001-12-04
申请号：US09477560
申请日：2000-01-04
申请人： Tomohisa Wada
发明人： Tomohisa Wada
IPC分类号： G11C1300
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1012 , G11C7/1027 , G11C7/1039 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C8/00 , G11C2207/2218 , G11C2207/2245
摘要： An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for external output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be improved.
摘要翻译：与要写入存储单元的数据对应的内部地址信号保持在锁存电路中。保持的内部地址信号由下一个写入操作中的多路复用器选择并应用于解码器。在从存储单元阵列未读出数据的期间，写入数据被锁存电路取入并保持。比较器比较保持的内部地址信号和用于读取数据的内部地址信号。如果它们之间发现匹配，则多路复用器从锁存电路输出数据以进行外部输出。因此，可以在不增加芯片成本，封装成本和系统成本的情况下消除读取操作之后的写入操作的延迟，从而实现高速缓存存储器的高速操作，并且实现诸如超级计算机，大型计算器，工作站和个人计算机可以改进。

7. 发明授权

US5724292A Static Semiconductor memory device 失效
标题翻译：静态半导体存储器件
公开(公告)号：US5724292A
公开(公告)日：1998-03-03
申请号：US781386
申请日：1997-01-13
申请人： Tomohisa Wada
发明人： Tomohisa Wada
IPC分类号： G11C11/413 , G11C11/419 , G11C7/02
CPC分类号： G11C11/419
摘要： Sense circuits are provided correspondingly to bit line pairs provided corresponding to memory cell columns, respectively. The sense circuit senses, amplifies and latches storage data of the selected memory cell, and information latched by the sense amplifier is rewritten into the selected memory cell after selection of the memory cell. Thereby, destruction of storage information of the memory cell is prevented.
摘要翻译：对应于分别对应于存储单元列提供的位线对提供感测电路。感测电路感测，放大和锁存所选择的存储单元的存储数据，并且在选择存储单元之后，读出放大器锁存的信息被重写到所选存储单元中。从而防止了存储单元的存储信息的破坏。

8. 发明授权

US5546352A Semiconductor memory device having decoder 失效
标题翻译：具有解码器的半导体存储器件
公开(公告)号：US5546352A
公开(公告)日：1996-08-13
申请号：US354760
申请日：1994-12-12
申请人： Hirotoshi Sato , Tomohisa Wada
发明人： Hirotoshi Sato , Tomohisa Wada
IPC分类号： G11C11/413 , G11C7/10 , G11C8/06 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/1051 , G11C8/06
摘要： In the present invention, a row address processing circuit and a column address processing circuit operate in synchronism with an externally applied synchronous signal in a semiconductor memory device. The row address processing circuit and the column address processing circuit each include an address buffer and a decoder. The address buffer or decoder operates in synchronism with the synchronous signal.
摘要翻译：在本发明中，行地址处理电路和列地址处理电路与半导体存储器件中外部施加的同步信号同步工作。行地址处理电路和列地址处理电路各自包括地址缓冲器和解码器。地址缓冲器或解码器与同步信号同步工作。

9. 发明授权

US5515325A Synchronous random access memory 失效
标题翻译：同步随机存取存储器
公开(公告)号：US5515325A
公开(公告)日：1996-05-07
申请号：US354767
申请日：1994-12-12
申请人： Tomohisa Wada
发明人： Tomohisa Wada
IPC分类号： G11C11/413 , G11C7/10 , G11C8/00 , G11C11/401 , G11C11/407 , G11C13/00
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1012 , G11C7/1027 , G11C7/1039 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C8/00 , G11C2207/2218 , G11C2207/2245
摘要： An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for externally output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputer, large size calculator, work station and personal computer can be improved.
摘要翻译：与要写入存储单元的数据对应的内部地址信号保持在锁存电路中。保持的内部地址信号由下一个写入操作中的多路复用器选择并应用于解码器。在从存储单元阵列未读出数据的期间，写入数据被锁存电路取入并保持。比较器比较保持的内部地址信号和用于读取数据的内部地址信号。如果在它们之间找到匹配，则多路复用器从锁存电路输出数据以进行外部输出。因此，可以在不增加芯片成本，封装成本和系统成本的情况下消除读取操作之后的写入操作的延迟，从而实现高速缓冲存储器的高速操作以及诸如超级计算机等各种级别的计算机的速度性能，大型计算器，工作台和个人电脑可以改进。

10. 发明授权

US5487041A Semiconductor memory device which can be programmed to indicate defective memory cell 失效
标题翻译：半导体存储器件，其可被编程以指示有缺陷的存储器单元
公开(公告)号：US5487041A
公开(公告)日：1996-01-23
申请号：US309823
申请日：1994-09-21
申请人： Tomohisa Wada
发明人： Tomohisa Wada
IPC分类号： G11C11/41 , G06F12/08 , G11C11/413 , G11C29/00 , G11C29/04 , G11C13/00
CPC分类号： G11C29/84 , G11C29/832
摘要： A cache memory device includes a plurality of memory cell arrays each including a plurality of memory cell rows, a plurality of first fuse elements each provided corresponding to each memory cell row and disconnected when the corresponding memory cell row is defective, and a plurality of second fuse elements each provided corresponding to each memory cell array and disconnected when the corresponding memory cell array is defective. As a result, the cache memory device can indicate that, when a bit line of a certain memory cell array is defective, the memory cell array is defective by disconnecting a second fuse element corresponding to the memory cell array.
摘要翻译：高速缓冲存储器装置包括多个存储单元阵列，每个存储单元阵列包括多个存储单元行，多个第一熔丝元件，每个第一熔丝元件对应于每个存储单元行设置，并且当相应的存储单元行有缺陷时被断开;多个第二熔丝元件每个熔丝元件对应于每个存储单元阵列，并且当对应的存储单元阵列有缺陷时断开。结果，高速缓冲存储器件可以指示当某个存储单元阵列的位线有缺陷时，通过断开与存储单元阵列相对应的第二熔丝元件，存储单元阵列有缺陷。

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