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1. 发明授权

US4992845A Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line 失效
标题翻译：具有输入/输出缓冲单元的半导体集成电路器件，每个单元包括排列成一行的多个晶体管区域
公开(公告)号：US4992845A
公开(公告)日：1991-02-12
申请号：US294020
申请日：1989-01-06
申请人： Takahiko Arakawa , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Masahiro Ueda , Yoshihiro Okuno
发明人： Takahiko Arakawa , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Masahiro Ueda , Yoshihiro Okuno
IPC分类号： H01L21/82 , H01L27/118
CPC分类号： H01L27/11898
摘要： An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).
摘要翻译：在半导体芯片（1）的中央部分设置有内部逻辑门部（3），设置有用于包围内部逻辑门部（3）的输入/输出缓冲器（4），并且提供接合焊盘（2）在对应于输入/输出缓冲器中的输入/输出缓冲单元（5）的半导体芯片（1）的外围部分中。每个输入/输出缓冲器单元（5）包括输出P-MOS部分（6），输出N-MOS部分（7），输入/逻辑P-MOS部分（8）和输入/ MOS部分（9），它们在从接合焊盘（2）到内部逻辑门部分（3）的方向上分别布置成单行。在上述结构中，键合焊盘（2）的焊盘布置方向上的输入/输出缓冲单元（5）中的每一个的尺寸减小，从而可以根据减少每个输入/输出缓冲单元（5）所需的排列方向的空间的使用。

2. 发明授权

US4916385A Inverter circuit 失效
标题翻译：逆变电路
公开(公告)号：US4916385A
公开(公告)日：1990-04-10
申请号：US262302
申请日：1988-10-25
申请人： Ichiro Tomioka , Masahiro Ueda , Takahiko Arakawa , Toshiaki Hanibuchi , Yoshihiro Okuno
发明人： Ichiro Tomioka , Masahiro Ueda , Takahiko Arakawa , Toshiaki Hanibuchi , Yoshihiro Okuno
IPC分类号： G01R19/165 , G01R31/316 , G01R31/317 , G01R31/319 , H03K17/00 , H03K17/16 , H03K19/003 , H03K19/0948
CPC分类号： H03K19/00361 , G01R31/316 , G01R31/31905
摘要： An inverter circuit (I.sub.3) is disclosed which includes a P-channel MOSFET (3) and a N-channel MOSFET (4) connected in series between a power supply (V.sub.DD) and a ground (GND). The inverter circuit further includes a P-channel MOSFET (5) and a N-channel MOSFET (6) connected in parallel between the gates of the FETs (3) and (4). The FETs (3) and (4) have their gates connected to receive testing mode signals (T.sub.E). In a testing mode operation, the FET (6) is rendered conductive to allow an input signal to be applied to the gate of the FET (4) through the FET (6). The FET (4), having an on-resistance lower than the FET (3), is driven into conduction in response to the output signal applied through the FET (6), thereby providing a slowly rising output signal. The slow rising output signal is free from undershoot or ringing.
摘要翻译：公开了一种逆变器电路（I3），其包括串联连接在电源（VDD）和地（GND）之间的P沟道MOSFET（3）和N沟道MOSFET（4）。逆变器电路还包括在FET（3）和（4）的栅极之间并联连接的P沟道MOSFET（5）和N沟道MOSFET（6）。 FET（3）和（4）的栅极连接以接收测试模式信号（TE）。在测试模式操作中，使FET（6）导通以允许通过FET（6）将输入信号施加到FET（4）的栅极。响应于通过FET（6）施加的输出信号，具有低于FET（3）的导通电阻的FET（4）被驱动成导通，从而提供缓慢上升的输出信号。缓慢上升的输出信号没有下冲或振铃。

3. 发明授权

US4848912A Apparatus for measuring a shape 失效
标题翻译：用于测量形状的装置
公开(公告)号：US4848912A
公开(公告)日：1989-07-18
申请号：US149607
申请日：1988-01-28
申请人： Kazuo Sano , Mitsuaki Uesugi , Masami Harayama , Yoshihiro Okuno , Hiroshi Matsunaga , Yoichi Matsuju
发明人： Kazuo Sano , Mitsuaki Uesugi , Masami Harayama , Yoshihiro Okuno , Hiroshi Matsunaga , Yoichi Matsuju
IPC分类号： G01B11/24 , G01B11/245
CPC分类号： G01B11/245
摘要： An apparatus for measuring shapes, comprises a scanner, having a plurality of arms for holding an object the shape of which is to be measured, and a turntable to which one end of each of the arms is fixed; and a device for forming a silhouette image of the object including a first optical system which has an optical axis parallel to a rotating axis of the turntable and which has a light source and a light receiving unit confronting each other to allow the object to be in between the light source and the light receiving unit of the first optical system, and a second optical system which has another optical axis substantially at a right angle to the rotating axis of the turntable and which has another light source and another light receiving unit confronting each other to allow the object to be in between the light source and the light receiving unit of the second optical system. A calculating device calculates a shape of the object, based on electric signals converted from an intensity pattern of light which has been formed by the device for forming a silhouette image of the object.

4. 发明申请

US20100179976A1 SEMICONDUCTOR DEVICE PERFORMING OPERATIONAL PROCESSING 审中-公开
标题翻译：执行操作处理的半导体器件
公开(公告)号：US20100179976A1
公开(公告)日：2010-07-15
申请号：US12687756
申请日：2010-01-14
申请人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
发明人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
IPC分类号： G06F7/44 , G06F5/01 , G06F7/552
CPC分类号： G06F7/5235 , G06F7/5324 , G06F7/5338
摘要： A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data.
摘要翻译：半导体器件包括：解码器，接收根据布斯（Booth）算法的3比特的第一乘法器数据，指示乘法器输出移位标志，反转标志和操作标志，第一部分乘积计算单元接收2位的第一被乘数数据指示被乘数，移位标志，反转标志和操作标志，以基于移位标志来选择第一被乘数数据的高位位和低位位之一，基于该选择位反转或非反转所选位反转标志，基于操作标志选择反相或非反相数据和预定逻辑电平的数据之一，并将选择的数据作为指示第一乘法器数据和第一被乘数数据的部分乘积的部分乘积数据输出。

5. 发明授权

US08042815B2 Cylinder head gasket and engine 有权
标题翻译：气缸盖垫片和发动机
公开(公告)号：US08042815B2
公开(公告)日：2011-10-25
申请号：US12524497
申请日：2008-01-31
申请人： Yoshihiro Okuno , Kazuya Yoshijima , Tsutomu Endou , Tetsuya Hida
发明人： Yoshihiro Okuno , Kazuya Yoshijima , Tsutomu Endou , Tetsuya Hida
IPC分类号： F02F11/00
CPC分类号： F16J15/0825
摘要： The thickness of an intermediate plate portion (31b) is smaller than the thickness of a stopper portion (31a). The thickness of a portion of a cylinder head gasket (20) having the stopper portion (31a) is set to be greater than the thickness of other portions of the cylinder head gasket (20). Before the cylinder head gasket (20) is provided between contact surfaces (12a, 13a), a space (S) is formed between the stopper portion (31a) and an adjustment stopper portion (32a), and the intermediate plate portion (31b) partially contacts the adjustment plate portion, and a bead (33a) contacts the adjustment plate portion (32b).
摘要翻译：中间板部（31b）的厚度小于止动部（31a）的厚度。具有止动部（31a）的气缸盖衬垫（20）的一部分的厚度被设定为大于气缸盖衬垫（20）的其他部分的厚度。在气缸盖衬垫（20）设置在接触表面（12a，13a）之前，在止动部分（31a）和调节止挡部分（32a）之间形成空间（S），中间板部分（31b）部分地接触调节板部分，并且胎圈（33a）接触调节板部分（32b）。

6. 发明申请

US20100117306A1 CYLINDER HEAD GASKET AND ENGINE 有权
标题翻译：气缸盖和发动机
公开(公告)号：US20100117306A1
公开(公告)日：2010-05-13
申请号：US12524497
申请日：2008-01-31
申请人： Yoshihiro Okuno , Kazuya Yoshijima , Tsutomu Endou , Tetsuya Hida
发明人： Yoshihiro Okuno , Kazuya Yoshijima , Tsutomu Endou , Tetsuya Hida
IPC分类号： F02F11/00
CPC分类号： F16J15/0825
摘要： The thickness of an intermediate plate portion (31b) is smaller than the thickness of a stopper portion (31a). The thickness of a portion of a cylinder head gasket (20) having the stopper portion (31a) is set to be greater than the thickness of other portions of the cylinder head gasket (20). Before the cylinder head gasket (20) is provided between contact surfaces (12a, 13a), a space (S) is formed between the stopper portion (31a) and an adjustment stopper portion (32a), and the intermediate plate portion (31b) partially contacts the adjustment plate portion, and a bead (33a) contacts the adjustment plate portion (32b).
摘要翻译：中间板部（31b）的厚度小于止动部（31a）的厚度。具有止动部（31a）的气缸盖衬垫（20）的一部分的厚度被设定为大于气缸盖衬垫（20）的其他部分的厚度。在气缸盖衬垫（20）设置在接触表面（12a，13a）之前，在止动部分（31a）和调节止挡部分（32a）之间形成空间（S），中间板部分（31b）部分地接触调节板部分，并且胎圈（33a）接触调节板部分（32b）。

7. 发明授权

US4923043A Air cooling system for clutch 失效
标题翻译：离合器空气冷却系统
公开(公告)号：US4923043A
公开(公告)日：1990-05-08
申请号：US237461
申请日：1988-08-29
申请人： Yoshihiro Okuno
发明人： Yoshihiro Okuno
IPC分类号： F16D13/72
CPC分类号： F16D13/72
摘要： A first baffle plate is approximately annular and disc-like, and one side of the plate is close to and faces on an engine block side face of a flywheel and an outer periphery of the plate is close to and faces on an inner peripheral surface of a clutch housing. A second baffle plate is approximately annular and disc-like, and one side of the plate is close to and faces on an opposite-to-pressure-plate side face of a clutch cover and an outer periphery of the plate is close to and faces on the inner peripheral surface of the clutch housing. A through hole penetrating the flywheel in its axial direction is formed on the flywheel at a position around an inner periphery of the first baffle plate. There formed on the clutch housing a first air inlet port positioned nearer to the engine block side than the part fronting on the outer periphery of the first baffle plate, an air outlet port positioned between the part fronting on the outer periphery of the first baffle plate and the part fronting on the outer periphery of the second baffle plate, and a second air inlet port positioned nearer to a side opposite to the engine block than the part fronting on the outer periphery of the second baffle plate.
摘要翻译：第一挡板大致呈圆环形，盘状，板的一侧靠近并面对飞轮的发动机缸体侧面，并且板的外周面靠近并面向内周面离合器壳体。第二挡板大致呈圆环形，盘状，板的一侧靠近并面对离合器盖的相对压板侧面，板的外周接近面在离合器壳体的内周面上。在飞轮上在第一挡板的内周围的位置处形成贯穿飞轮的轴向通孔。在离合器上形成的第一空气入口位于比第一挡板的外周上的部分更靠近发动机缸体侧的第一空气入口，位于第一挡板的外周面之间的部分之间的出气口以及位于第二挡板的外周上的部分以及位于比第二挡板的外周上的部分更靠近发动机缸体侧的第二空气入口。

8. 发明授权

US4999698A Interconnection arrangement for a gate array 失效
标题翻译：门阵列的互连布置
公开(公告)号：US4999698A
公开(公告)日：1991-03-12
申请号：US394329
申请日：1989-08-16
申请人： Yoshihiro Okuno , Yohichi Kuramitsu
发明人： Yoshihiro Okuno , Yohichi Kuramitsu
IPC分类号： H01L21/822 , H01L21/82 , H01L23/528 , H01L27/04 , H01L27/118
CPC分类号： H01L23/528 , H01L27/11807 , H01L2924/0002
摘要： An improved carpeting gate array having a plurality of basic cells (9) each comprising an N channel MOS transistor (8) and a P channel MOS transistor (7) continuously arranged in row and column directions comprises a logic cell region (20) comprising a plurality of basic cells (9) continuously formed in a channel width direction (a direction intersecting with a direction in which their gate electrodes (4) of a plurality of N channel or P channel MOS transistors are continuously arranged spaced apart from each other), and an interconnection region (21) for providing interconnections to the logic cells (20) continuously formed in the channel width direction. The size in a width direction of the interconnection region is defined by the size in a channel length direction (a direction intersecting with the channel width direction) of the basic cells (9).
摘要翻译：一种具有多个基本单元（9）的改进的地毯门阵列，每个基本单元包括以行和列方向连续排列的N沟道MOS晶体管（8）和P沟道MOS晶体管（7），包括一个逻辑单元区域（20）在沟道宽度方向（与多个N沟道或P沟道MOS晶体管的栅极（4）彼此间隔开连接的方向相交的方向）连续形成的多个基本单元（9）以及用于向在通道宽度方向上连续形成的逻辑单元（20）提供互连的互连区域（21）。互连区域的宽度方向的大小由基体单元（9）的沟道长度方向（与沟道宽度方向相交的方向）的大小决定。

9. 发明授权

US4221930A FM Defect compensation apparatus 失效
标题翻译： FM缺陷补偿装置
公开(公告)号：US4221930A
公开(公告)日：1980-09-09
申请号：US29152
申请日：1979-04-11
申请人： Yoshihiro Okuno
发明人： Yoshihiro Okuno
IPC分类号： H04B1/10 , G11B20/06 , H03G3/34 , H03G5/18 , H04S1/00 , H04N5/76
CPC分类号： H03G3/345 , H03G5/18
摘要： In systems which process frequency modulated carrier waves, such as video disc systems, video tape recorder/playback systems and radio systems, there are occasions where the FM signal suddenly drops to a low level. In the case of FM audio signals, these sudden drops result in objectionable tics and pops in the demodulated audio output. The apparatus described herein reduces these objectionable noises by utilizing a variable impedance in connection with a deemphasis circuit in the main signal path. Upon the occurrence of a signal dropout, a defect indication signal is provided to the variable impedance device. The deemphasis circuit has an overall time constant which includes the variable impedance device and which varies in accordance with the detected signal dropouts so as to provide a substantially smooth demodulated output signal whereby tics and pops, in the output audio signal, are substantially removed.
摘要翻译：在处理频率调制载波的系统中，例如视频盘系统，录像机/回放系统和无线电系统，有时候FM信号突然降低到低电平。在FM音频信号的情况下，这些突然的下降导致在解调的音频输出中令人反感的抽搐和流淌。本文描述的装置通过利用与主信号路径中的去加重电路相关的可变阻抗来减少这些令人不快的噪声。在出现信号丢失时，向可变阻抗装置提供缺陷指示信号。去加重电路具有总时间常数，其包括可变阻抗装置，并且其根据检测到的信号丢失而变化，以便提供基本平滑的解调输出信号，从而基本上去除输出音频信号中的抽搐和流出。

10. 发明授权

US08325609B2 Data processing device 失效
标题翻译：数据处理装置
公开(公告)号：US08325609B2
公开(公告)日：2012-12-04
申请号：US12847439
申请日：2010-07-30
申请人： Masami Nakajima , Yoshihiro Okuno
发明人： Masami Nakajima , Yoshihiro Okuno
IPC分类号： G08C15/00 , H04L12/56 , H04J3/04
CPC分类号： H04L47/125 , G06F11/1415 , G06F11/1423
摘要： This invention provides a data processing device capable of operating a plurality of processing modules in parallel. Processes following a processing flow are assigned to the plural processing modules, respectively, and at least two of the processing modules are capable of running a same process. A network includes an arbitration circuit that, upon receiving a packet from a processing module, according to a process number attached to the packet, selects a processing module out of the processing modules capable of running the process, and outputs the packet to the selected processing module. This thus allows for autonomous transfer of a packet between each processing module and makes it possible to operate the processing modules in parallel.
摘要翻译：本发明提供了能够并行地操作多个处理模块的数据处理装置。处理流程之后的处理分别分配给多个处理模块，并且至少两个处理模块能够运行相同的处理。网络包括仲裁电路，在从处理模块接收到分组后，根据附加到分组的处理号码，从能够运行该处理的处理模块中选择处理模块，并将该分组输出到所选择的处理模块。因此，这允许在每个处理模块之间自动传送分组，并且使得可以并行地操作处理模块。

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