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    • 3. 发明授权
    • Semiconductor memory device and word line driving method thereof
    • 半导体存储器件及其字线驱动方法
    • US07948823B2
    • 2011-05-24
    • US12344629
    • 2008-12-29
    • Tae-Sik YunKang-Seol Lee
    • Tae-Sik YunKang-Seol Lee
    • G11C8/00
    • G11C8/10G11C8/08
    • A semiconductor memory device having a plurality of cell blocks includes: a block decoding unit configured to decode an input address for selecting a corresponding cell block to generate a block selection signal; a block information address generating unit configured to perform a logic operation on the block selection signal and an assignment address for selecting a word line to be activated within the corresponding cell block to generate a block information address activated only when the corresponding cell block is selected; and a word line driving unit configured to select a word line in response to the block information address.
    • 具有多个单元块的半导体存储器件包括:块解码单元,被配置为对用于选择相应的单元块的输入地址进行解码以产生块选择信号; 块信息地址生成单元,被配置为对块选择信号执行逻辑运算,以及分配地址,用于选择要在相应的单元块内激活的字线,以产生只有当相应的单元块被选择时激活的块信息地址; 以及字线驱动单元,被配置为响应于块信息地址来选择字线。
    • 5. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME
    • 半导体存储器件及其驱动方法
    • US20110158023A1
    • 2011-06-30
    • US12829987
    • 2010-07-02
    • Tae-Sik YunKang-Seol Lee
    • Tae-Sik YunKang-Seol Lee
    • G11C7/06
    • G11C11/4091G11C7/08G11C7/1048G11C11/4087G11C2207/005
    • A semiconductor memory device includes a cell block including a first bit line, a sense amplifier unit including a second bit line and configured to amplify a data signal applied to the second bit line, a connection unit configured to selectively connect the first bit line and the second bit line, a connection control unit configured to receive a control signal for driving the sense amplifier unit and a selection signal for selecting the cell block and generate a connection signal for activating the connection unit at a first time, and a sense amplifier driving control unit configured to receive the control signal and generate a sense amplifier driving signal for driving the sense amplifier unit at a second time after the first time.
    • 半导体存储器件包括:包括第一位线的单元块,包括第二位线的读出放大器单元,用于放大施加到第二位线的数据信号;连接单元,被配置为选择性地将第一位线和 第二位线,连接控制单元,被配置为接收用于驱动读出放大器单元的控制信号和用于选择单元块的选择信号,并且在第一时间产生用于激活连接单元的连接信号,以及读出放大器驱动控制 被配置为接收控制信号并且在第一次之后的第二时间产生用于驱动读出放大器单元的读出放大器驱动信号。
    • 6. 发明授权
    • Semiconductor memory device and method for driving the same
    • 半导体存储器件及其驱动方法
    • US08213251B2
    • 2012-07-03
    • US12829987
    • 2010-07-02
    • Tae-Sik YunKang-Seol Lee
    • Tae-Sik YunKang-Seol Lee
    • G11C7/02
    • G11C11/4091G11C7/08G11C7/1048G11C11/4087G11C2207/005
    • A semiconductor memory device includes a cell block including a first bit line, a sense amplifier unit including a second bit line and configured to amplify a data signal applied to the second bit line, a connection unit configured to selectively connect the first bit line and the second bit line, a connection control unit configured to receive a control signal for driving the sense amplifier unit and a selection signal for selecting the cell block and generate a connection signal for activating the connection unit at a first time, and a sense amplifier driving control unit configured to receive the control signal and generate a sense amplifier driving signal for driving the sense amplifier unit at a second time after the first time.
    • 半导体存储器件包括:包括第一位线的单元块,包括第二位线的读出放大器单元,用于放大施加到第二位线的数据信号;连接单元,被配置为选择性地将第一位线和 第二位线,连接控制单元,被配置为接收用于驱动读出放大器单元的控制信号和用于选择单元块的选择信号,并且在第一时间产生用于激活连接单元的连接信号,以及读出放大器驱动控制 被配置为接收控制信号并且在第一次之后的第二时间产生用于驱动读出放大器单元的读出放大器驱动信号。
    • 9. 发明授权
    • Semiconductor integrated circuit having stacked semiconductor chips and vias therebetween
    • 半导体集成电路具有堆叠的半导体芯片和它们之间的通孔
    • US08441831B2
    • 2013-05-14
    • US12878347
    • 2010-09-09
    • Young-Jun KuTae-Sik Yun
    • Young-Jun KuTae-Sik Yun
    • G11C5/06
    • H01L23/522G06F2213/0038H01L23/481H01L25/0657H01L2225/06513H01L2225/06544H01L2924/0002H04J3/047H04L25/028H04L25/0292H01L2924/00H01L2924/00012
    • A semiconductor integrated circuit includes a first semiconductor chip including a first output circuit which is enabled in a first operation mode and outputs a first output signal and a second output circuit which is enabled in a second operation mode and outputs a second output signal; a second semiconductor chip including a first input circuit which is enabled in the first operation mode and receives the first output signal and a second input circuit which is enabled in the second operation mode and receives the second output signal; and a common through chip via arranged to vertically penetrate through the semiconductor chip, be coupled with the first and second output circuits in one end and coupled with the first and second input circuits in the other end, and interface transfer of the first and second output signals which are enabled in different operation modes, including the first and second operation modes.
    • 一种半导体集成电路包括:第一半导体芯片,包括第一输出电路,其在第一操作模式下使能并输出第一输出信号;以及第二输出电路,其在第二操作模式下被使能并输出第二输出信号; 第二半导体芯片,包括在第一操作模式中被使能并接收第一输出信号的第一输入电路和在第二操作模式中被使能并接收第二输出信号的第二输入电路; 并且布置成垂直穿过半导体芯片的通用芯片通孔在一端与第一和第二输出电路耦合,并在另一端与第一和第二输入电路耦合,并且第一和第二输出 在不同的操作模式下启用的信号,包括第一和第二操作模式。