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1. 发明申请

US20220137182A1 MULTIPLE CHIRP GENERATION IN A RADAR SYSTEM 有权
公开(公告)号：US20220137182A1
公开(公告)日：2022-05-05
申请号：US17574680
申请日：2022-01-13
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Tom Altus , Jasbir Singh Nayyar , Karthik Ramasubramanian , Brian Paul Ginsburg
IPC分类号： G01S7/35 , G01S13/34
摘要： A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

2. 发明授权

US11486916B2 Frequency synthesizer output cycle counter including ring encoder 有权
公开(公告)号：US11486916B2
公开(公告)日：2022-11-01
申请号：US17515637
申请日：2021-11-01
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Tom Altus , Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
IPC分类号： G01R23/02 , G01R23/10 , H03L7/091
摘要： A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

3. 发明授权

US10481187B2 Frequency synthesizer output cycle counter including ring encoder 有权
公开(公告)号：US10481187B2
公开(公告)日：2019-11-19
申请号：US14588014
申请日：2014-12-31
申请人： Texas Instruments Incorporated
发明人： Tom Altus , Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
IPC分类号： G01R23/02 , G01R23/10 , H03L7/091
摘要： A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

4. 发明申请

US20200041551A1 FREQUENCY SYNTHESIZER OUTPUT CYCLE COUNTER INCLUDING RING ENCODER 审中-公开
公开(公告)号：US20200041551A1
公开(公告)日：2020-02-06
申请号：US16597612
申请日：2019-10-09
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Tom Altus , Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
IPC分类号： G01R23/02 , G01R23/10
摘要： A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

5. 发明申请

US20180203096A1 MULTIPLE CHIRP GENERATION IN A RADAR SYSTEM 审中-公开
公开(公告)号：US20180203096A1
公开(公告)日：2018-07-19
申请号：US15921887
申请日：2018-03-15
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Tom Altus , Jasbir Singh Nayyar , Karthik Ramasubramanian , Brian Paul Ginsburg
IPC分类号： G01S7/35 , G01S13/34
CPC分类号： G01S7/35 , G01S13/34 , G01S13/343
摘要： A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

6. 发明授权

US09921295B2 Multiple chirp generation in a radar system 有权
公开(公告)号：US09921295B2
公开(公告)日：2018-03-20
申请号：US14586854
申请日：2014-12-30
申请人： Texas Instruments Incorporated
发明人： Tom Altus , Jasbir Singh Nayyar , Karthik Ramasubramanian , Brian Paul Ginsburg
IPC分类号： G01S7/282 , G01S7/35 , G01S13/34
CPC分类号： G01S7/35 , G01S13/34 , G01S13/343
摘要： A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

7. 发明申请

US20160187462A1 Multiple Chirp Generation in a Radar System 有权
标题翻译：雷达系统中的多个啁啾声发生
公开(公告)号：US20160187462A1
公开(公告)日：2016-06-30
申请号：US14586854
申请日：2014-12-30
申请人： Texas Instruments Incorporated
发明人： Tom Altus , Jasbir Singh Nayyar , Karthik Ramasubramanian , Brian Paul Ginsburg
IPC分类号： G01S7/28 , G01S13/02
CPC分类号： G01S7/35 , G01S13/34 , G01S13/343
摘要： A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.
摘要翻译：提供一种雷达装置，其包括定时控制部件，所述定时控制部件可操作以根据啁啾配置参数的一组啁啾配置参数的每个啁啾和啁啾啁啾分布来产生啁啾控制信号，以使雷达装置发送啁啾，具有啁啾配置参数输入，啁啾剖面参数输入，啁啾地址输出和啁啾控制信号输出的定时控制组件，啁啾配置存储组件，其具有连接到定时的配置参数输入的相应输入的啁啾配置参数输出控制组件，啁啾配置文件地址输出和耦合到啁啾地址输出的啁啾地址输入，以及啁啾配置文件存储组件，其具有耦合到定时控制组件的啁啾剖面参数输入的啁啾分布参数输出; 以及耦合到啁啾配置文件地址输出的啁啾配置文件地址输入。

8. 发明授权

US11927690B2 Multiple chirp generation in a radar system 有权
公开(公告)号：US11927690B2
公开(公告)日：2024-03-12
申请号：US17574680
申请日：2022-01-13
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Tom Altus , Jasbir Singh Nayyar , Karthik Ramasubramanian , Brian Paul Ginsburg
IPC分类号： G01S7/35 , G01S13/34
CPC分类号： G01S7/35 , G01S13/34 , G01S13/343
摘要： A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

9. 发明授权

US11262435B2 Multiple chirp generation in a radar system 有权
公开(公告)号：US11262435B2
公开(公告)日：2022-03-01
申请号：US15921887
申请日：2018-03-15
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Tom Altus , Jasbir Singh Nayyar , Karthik Ramasubramanian , Brian Paul Ginsburg
IPC分类号： G01S7/35 , G01S13/34
摘要： A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

10. 发明授权

US11162986B2 Frequency synthesizer output cycle counter including ring encoder 有权
公开(公告)号：US11162986B2
公开(公告)日：2021-11-02
申请号：US16597612
申请日：2019-10-09
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Tom Altus , Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
IPC分类号： G01R23/02 , G01R23/10 , H03L7/091
摘要： A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

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