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1. 发明申请

US20140266361A1 DUTY CYCLE CORRECTION CIRCUIT 审中-公开
标题翻译：占空比校正电路
公开(公告)号：US20140266361A1
公开(公告)日：2014-09-18
申请号：US13886637
申请日：2013-05-03
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Siddharth Shashidharan , Sumantra Seth , Ravi Jithendra Mehta , Biman Chattopadhyay , Sujoy Chinmoy Chakravarty
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： In an embodiment, a duty cycle correction circuit comprises a first set of inverters connected in series, a first filter, a first feedback circuit and a second feedback circuit. A first inverter in the series is configured to receive a clock signal and a last inverter in the series is configured to provide a first output clock signal. The first filter is configured to generate a first direct current (DC) voltage signal at an output of the first filter. The first feedback circuit is configured to control a rise time of a signal transition at an output terminal of the first inverter to control a duty cycle of the first output clock cycle. The second feedback circuit is configured to control a fall time of the signal transition at the output terminal of the first inverter to control the duty cycle of the first output clock cycle.
摘要翻译：在一个实施例中，占空比校正电路包括串联连接的第一组反相器，第一滤波器，第一反馈电路和第二反馈电路。串联的第一反相器被配置为接收时钟信号，并且串联中的最后一个反相器被配置为提供第一输出时钟信号。第一滤波器被配置为在第一滤波器的输出处产生第一直流（DC）电压信号。第一反馈电路被配置为控制第一反相器的输出端处的信号转变的上升时间，以控制第一输出时钟周期的占空比。第二反馈电路被配置为控制第一反相器的输出端处的信号转变的下降时间，以控制第一输出时钟周期的占空比。

2. 发明授权

US09407424B1 Fast locking clock and data recovery using only two samples per period 有权
标题翻译：快速锁定时钟和数据恢复，每个周期只使用两个样本
公开(公告)号：US09407424B1
公开(公告)日：2016-08-02
申请号：US14682249
申请日：2015-04-09
申请人： Texas Instruments Incorporated
发明人： Bharathi Rahuldev Holla , Jagdish Chand Goyal , Biman Chattopadhyay , Sujoy Chakravarty , Sumantra Seth
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H04L7/0004
摘要： A clock and data recovery module (CDR) is configured to perform fast locking using only two samples per each unit interval (UI). Two clock phase signals are selected from a plurality of clock phase signals. A sequence of data bits is sampled at a rate of two times per UI responsive to the two clock phase signals in which a first sample of each UI is designated as an edge sample a second sample is designated as a data sample. Each edge sample is voted as early/late as compared to an associated data transition of the sequence of data bits by comparing each edge sample to a next data sample. The sample clocks are locked such that edge samples occur in proximity to data transitions by iteratively adjusting a phase of the two selected clock phase signals by a variable step size in response to the early/late vote.
摘要翻译：时钟和数据恢复模块（CDR）被配置为使用每个单位间隔（UI）仅使用两个采样来执行快速锁定。从多个时钟相位信号中选择两个时钟相位信号。响应于两个时钟相位信号，以每个UI两倍的速率对数据比特序列进行采样，其中将每个UI的第一样本指定为边缘样本，将第二样本指定为数据样本。通过将每个边缘样本与下一个数据样本进行比较，与数据比特序列的相关数据转换相比，每个边缘样本被提前/晚选。采样时钟被锁定，使得边缘采样在数据转换附近发生，通过响应于早/晚表决反复调整两个所选择的时钟相位信号的相位可变步长。

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