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1. 发明授权

US11967621B2 Silicide-sandwiched source/drain region and method of fabricating same 有权
公开(公告)号：US11967621B2
公开(公告)日：2024-04-23
申请号：US18155887
申请日：2023-01-18
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chung-Hui Chen , Tung-Tsun Chen , Jui-Cheng Huang
IPC分类号： H01L29/417 , H01L21/8234 , H01L21/8238 , H01L29/08 , H01L29/40 , H01L29/49 , H01L29/66 , H01L29/78 , H01L29/786 , H01L23/34 , H01L27/06
CPC分类号： H01L29/4175 , H01L21/823418 , H01L21/823475 , H01L21/823814 , H01L29/0847 , H01L29/401 , H01L29/41725 , H01L29/41766 , H01L29/4933 , H01L29/665 , H01L29/7845 , H01L29/78618 , H01L23/345 , H01L27/0629
摘要： A method of manufacturing a semiconductor structure includes forming an active region having a first portion which is doped. The method further includes forming a first silicide layer over and electrically coupled to the first portion of the active region. The method further includes forming a second silicide layer under and electrically coupled to the first portion of the active region. The method further includes forming a first metal-to-drain/source (MD) contact structure over and electrically coupled to the first silicide layer. The method further includes forming a first via-to-MD (VD) structure over and electrically coupled to the MD contact structure. The method further includes forming a buried via-to-source/drain (BVD) structure under and electrically coupled to the second silicide layer.

2. 发明授权

US11901289B2 Semiconductor device structure with resistive element 有权
公开(公告)号：US11901289B2
公开(公告)日：2024-02-13
申请号：US17848146
申请日：2022-06-23
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Wan-Te Chen , Chung-Hui Chen , Wei-Chih Chen , Chii-Ping Chen , Wen-Sheh Huang , Bi-Ling Lin , Sheng-Feng Liu
IPC分类号： H01L23/522 , H01L27/06 , H01L23/367 , H01L29/423 , H01L29/78
CPC分类号： H01L23/5228 , H01L23/3677 , H01L27/0629 , H01L29/42376 , H01L29/78
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.

3. 发明授权

US11563095B2 Silicide-sandwiched source/drain region and method of fabricating same 有权
公开(公告)号：US11563095B2
公开(公告)日：2023-01-24
申请号：US17175064
申请日：2021-02-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chung-Hui Chen , Tung-Tsun Chen , Jui-Cheng Huang
IPC分类号： H01L29/417 , H01L29/08 , H01L29/40 , H01L29/786 , H01L29/49 , H01L29/78 , H01L21/8234 , H01L29/66 , H01L27/06 , H01L23/34
摘要： A semiconductor device including: a first S/D arrangement including a silicide-sandwiched portion of a corresponding active region having a silicide-sandwiched configuration, a first portion of a corresponding metal-to-drain/source (MD) contact structure, a first via-to-MD (VD) structure, and a first buried via-to-source/drain (BVD) structure; a gate structure over a channel portion of the corresponding active region; and a second S/D arrangement including a first doped portion of the corresponding active region; and at least one of the following: an upper contact arrangement including a first silicide layer over the first doped portion, a second portion of the corresponding MD contact structure; and a second VD structure; or a lower contact arrangement including a second silicide layer under the first doped portion, and a second BVD structure.

4. 发明申请

US20220405457A1 Standard Cell Design 有权
公开(公告)号：US20220405457A1
公开(公告)日：2022-12-22
申请号：US17476615
申请日：2021-09-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shu-Wei Chung , Tung-Heng Hsieh , Chung-Hui Chen , Chung-Yi Lin
IPC分类号： G06F30/392 , G06F30/398 , G06F30/323
摘要： An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

5. 发明申请

US20220278091A1 CIRCUITS DESIGNED AND MANUFACTURED WITH FIRST AND SECOND FIN BOUNDARIES 有权
公开(公告)号：US20220278091A1
公开(公告)日：2022-09-01
申请号：US17543255
申请日：2021-12-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chung-Hui Chen , Weichih Chen , Tien-Chien Huang , Chien-Chun Tsai , Ruey-Bin Sheen , Tsung-Hsin Yu , Chih-Hsien Chang , Cheng-Hsiang Hsieh
IPC分类号： H01L27/02 , H01L29/417 , H01L29/40 , H01L21/8234 , H01L27/088 , H03K17/687
摘要： A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.

6. 发明授权

US10396217B2 Decoupling finFET capacitors 有权
公开(公告)号：US10396217B2
公开(公告)日：2019-08-27
申请号：US15389173
申请日：2016-12-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chung-Hui Chen
IPC分类号： H01L21/762 , H01L49/02 , H01L29/94 , H01L29/66 , H01L27/08 , H01L27/06 , H01L27/088 , H01L29/78 , H01L27/12
摘要： A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.

7. 发明授权

US10354920B2 Methods and apparatus for MOS capacitors in replacement gate process 有权
公开(公告)号：US10354920B2
公开(公告)日：2019-07-16
申请号：US15231215
申请日：2016-08-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
IPC分类号： H01L27/07 , H01L21/822 , H01L21/8234 , H01L29/94 , H01L27/06 , H01L27/08 , H01L49/02 , H01L29/40
摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

8. 发明授权

US09911819B2 Circuits using gate-all-around technology 有权
公开(公告)号：US09911819B2
公开(公告)日：2018-03-06
申请号：US15479803
申请日：2017-04-05
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Chung-Hui Chen
IPC分类号： H01L29/06 , H01L29/423 , H01L27/088 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/42392 , H01L21/823487 , H01L27/0207 , H01L27/088 , H01L29/0676 , H01L29/66666 , H01L29/7827
摘要： A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first top OD region, a first bottom OD region, and a first nanowire. A second GAA transistor includes: a second top OD region, a second bottom OD region, and a second nanowire. The first top OD region, the first bottom OD region, and the first nanowire are symmetrical with the second top OD region, the second bottom OD region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow from the first top OD region to the first bottom OD region, and the second GAA transistor is arranged to provide a second current to flow from the second top OD region to the second bottom OD region.

9. 发明授权

US09627479B2 Circuits using gate-all-around technology 有权
公开(公告)号：US09627479B2
公开(公告)日：2017-04-18
申请号：US15048677
申请日：2016-02-19
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Chung-Hui Chen
IPC分类号： H01L29/06 , H01L27/088 , H01L29/78 , H01L27/02 , H01L29/423 , H01L29/66 , H01L21/8234
CPC分类号： H01L29/42392 , H01L21/823487 , H01L27/0207 , H01L27/088 , H01L29/0676 , H01L29/66666 , H01L29/7827
摘要： In some embodiments, a semiconductor structure includes first and second GAA structures configured to form corresponding similar first and second circuits. At least one of the first or second GAA structure includes at least one GAA device. A GAA device of the at least one GAA device includes at least one nanowire and a gate region. A nanowire of the at least one nanowire has a cross-section asymmetrical with respect to a middle line of the cross-section. The cross-section has first and second end lines substantially parallel the middle line. The first end line is shorter than the second end line. The gate region wraps all around part of the nanowire. The first and second GAA structures have substantially a same of a number of GAA devices in the at least one GAA device configured to have current flow from the first end line to the second end line.

10. 发明授权

US09502358B2 Integrated circuit having shielding structure 有权
标题翻译：具有屏蔽结构的集成电路
公开(公告)号：US09502358B2
公开(公告)日：2016-11-22
申请号：US14332986
申请日：2014-07-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chung-Hui Chen
IPC分类号： H01L29/40 , H01L23/552 , H01L23/522 , H01L27/02
CPC分类号： H01L23/552 , H01L23/5225 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a signal line and a plurality of shielding structures. The signal line is routed along a first direction and is in a first metallization layer. Each shielding structure includes a plurality of non-contiguous shielding patterns aligned along the first direction. The plurality of shielding structures includes a first and a second shielding structures in a second metallization layer that adjoins the first metallization layer and a third and a fourth shielding structures in a third metallization layer that adjoins the first metallization layer. The first metallization layer is between the second and the third metallization layers. The first and the second shielding structures are separated from each other along a second direction perpendicular to the first direction. The third and the fourth shielding structures are separated from each other along the second direction.
摘要翻译：集成电路包括信号线和多个屏蔽结构。信号线沿着第一方向布线并且处于第一金属化层中。每个屏蔽结构包括沿着第一方向排列的多个不连续的屏蔽图案。多个屏蔽结构包括邻接第一金属化层的第二金属化层中的第一和第二屏蔽结构以及邻接第一金属化层的第三金属化层中的第三和第四屏蔽结构。第一金属化层位于第二和第三金属化层之间。第一和第二屏蔽结构沿垂直于第一方向的第二方向彼此分离。第三和第四屏蔽结构沿第二方向彼此分离。

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