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1. 发明授权

US07502959B2 Error correction apparatus, systems, and methods 有权
标题翻译：纠错装置，系统和方法
公开(公告)号：US07502959B2
公开(公告)日：2009-03-10
申请号：US10628726
申请日：2003-07-28
申请人： Suresh Marisetty , George Thangadurai , Mani Ayyar
发明人： Suresh Marisetty , George Thangadurai , Mani Ayyar
IPC分类号： G06F11/00
CPC分类号： G06F11/2242
摘要： A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.
摘要翻译：一种系统包括非易失性存储器和多个处理器。非易失性存储器存储错误处理例程。多个处理器的每个处理器在检测到错误时访问错误处理例程，并且在某些错误时，信号剩余的处理器进入会合状态。在会合状态下，单个处理器接管并执行错误处理。

2. 发明授权

US06754828B1 Algorithm for non-volatile memory updates 有权
标题翻译：用于非易失性存储器更新的算法
公开(公告)号：US06754828B1
公开(公告)日：2004-06-22
申请号：US09352715
申请日：1999-07-13
申请人： Suresh Marisetty , Andrew J. Fish , Yan Li , Mani Ayyar , Amy O'Donnell , George Thangadurai , Sham M. Datta
发明人： Suresh Marisetty , Andrew J. Fish , Yan Li , Mani Ayyar , Amy O'Donnell , George Thangadurai , Sham M. Datta
IPC分类号： G06F942
CPC分类号： G06F8/65
摘要： A novel processor architecture and algorithms are provided which improve non-volatile memory updates and increases processor performance in successive generations of processors. A new processor architecture is supported by a software model consisting of two new firmware layers and the legacy 32 bit basic input output system (BIOS) firmware. The new firmware layers consist of a Processor Abstraction Layer (PAL) and a System Abstraction Layer (SAL). The PAL and SAL have procedure calls which allow updates of the firmware components in the non-volatile memory of a system, e.g. non-volatile ROM. The present invention includes invoking a system abstraction layer update procedure to implement a new input binary into the non-volatile memory. An algorithm for the non-volatile memory includes selecting a lead processor to perform an update and using the system abstraction layer update procedure. The system abstraction layer update procedure is used to call an appropriate authentication routine. The system abstraction layer update procedure is used to call a specific non-volatile memory implementation routine.
摘要翻译：提供了一种新颖的处理器架构和算法，其改进了非易失性存储器更新并且在连续几代处理器中提高了处理器性能。由两个新固件层和传统32位基本输入输出系统（BIOS）固件组成的软件模型支持新的处理器架构。新的固件层由处理器抽象层（PAL）和系统抽象层（SAL）组成。 PAL和SAL具有允许更新系统的非易失性存储器中的固件组件的过程调用，例如，非易失性ROM。本发明包括调用系统抽象层更新过程以将新的输入二进制文件实现到非易失性存储器中。用于非易失性存储器的算法包括选择引导处理器来执行更新并使用系统抽象层更新过程。系统抽象层更新过程用于调用适当的认证例程。系统抽象层更新过程用于调用特定的非易失性存储器实现例程。

3. 发明授权

US06675324B2 Rendezvous of processors with OS coordination 有权
标题翻译：处理器集合与操作系统协调
公开(公告)号：US06675324B2
公开(公告)日：2004-01-06
申请号：US09405972
申请日：1999-09-27
申请人： Suresh Marisetty , George Thangadurai , Mani Ayyar
发明人： Suresh Marisetty , George Thangadurai , Mani Ayyar
IPC分类号： G06F1100
CPC分类号： G06F11/2242
摘要： A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.
摘要翻译：一种系统包括非易失性存储器和多个处理器。非易失性存储器存储错误处理例程。多个处理器的每个处理器在检测到错误时访问错误处理例程，并且在某些错误时，信号剩余的处理器进入会合状态。在会合状态下，单个处理器接管并执行错误处理。

4. 发明授权

US06622260B1 System abstraction layer, processor abstraction layer, and operating system error handling 有权
标题翻译：系统抽象层，处理器抽象层和操作系统错误处理
公开(公告)号：US06622260B1
公开(公告)日：2003-09-16
申请号：US09475417
申请日：1999-12-30
申请人： Suresh Marisetty , Mani Ayyar , Nhon T. Quach , Bernard J. Lint
发明人： Suresh Marisetty , Mani Ayyar , Nhon T. Quach , Bernard J. Lint
IPC分类号： G06F1100
CPC分类号： G06F11/0724 , G06F11/0793
摘要： Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log. The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.
摘要翻译：公开了用于错误处理的系统和方法。系统和方法可以用于单处理器或多处理器计算机系统以硬件和任何固件或软件层之间协调的方式处理错误。计算机系统包括非易失性存储器和至少一个处理器。固件错误处理程序存储在非易失性存储器中。固件错误处理例程用于处理错误。所述至少一个处理器中的每一个检测错误。每个处理器在检测到错误时执行固件错误处理程序。执行的固件错误处理例程处理错误。执行的固件错误处理例程还将错误信息记录到日志中。系统和方法提供协调的错误处理，增强错误恢复，提供错误控制和维护系统可用性。

5. 发明授权

US07117396B2 Scalable CPU error recorder 失效
公开(公告)号：US07117396B2
公开(公告)日：2006-10-03
申请号：US10029308
申请日：2001-12-28
申请人： Eshwari P. Komarla , Suresh Marisetty , Mani Ayyar , Andrew J. Fish , Mohan J. Kumar , Shivnandan D. Kaushik
发明人： Eshwari P. Komarla , Suresh Marisetty , Mani Ayyar , Andrew J. Fish , Mohan J. Kumar , Shivnandan D. Kaushik
IPC分类号： G06F11/00
CPC分类号： G06F11/0787 , G06F11/073
摘要： A firmware-based mechanism for creating, storing and retrieving variable-length records associated with error events occurring in a computer platform. The mechanism responds to error notifications by invoking a firmware-based error-handling module. The error-handling module retrieves processor-specific error information and may also interrogate the other components of the computer platform to determine their error status. Then, according to the nature of the discovered errors, the error-handling module may assemble the retrieved error information and status information into a variable-length error record, which the error-handling module may then store in a memory. On request from a processing agent, the error-handling module may retrieve a previously-stored error record and present it to the requesting agent. Thus, the invention provides a unified and standardized approach to computer error handling at the firmware level.

6. 发明授权

US07904751B2 System abstraction layer, processor abstraction layer, and operating system error handling 有权
标题翻译：系统抽象层，处理器抽象层和操作系统错误处理
公开(公告)号：US07904751B2
公开(公告)日：2011-03-08
申请号：US10628769
申请日：2003-07-28
申请人： Suresh Marisetty , Mani Ayyar , Nhon T. Quach , Bernard J. Lint
发明人： Suresh Marisetty , Mani Ayyar , Nhon T. Quach , Bernard J. Lint
IPC分类号： G06F11/00
CPC分类号： G06F11/0724 , G06F11/0793
摘要： Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log.The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.
摘要翻译：公开了用于错误处理的系统和方法。系统和方法可以用于单处理器或多处理器计算机系统以硬件和任何固件或软件层之间协调的方式处理错误。计算机系统包括非易失性存储器和至少一个处理器。固件错误处理程序存储在非易失性存储器中。固件错误处理例程用于处理错误。所述至少一个处理器中的每一个检测错误。每个处理器在检测到错误时执行固件错误处理程序。执行的固件错误处理例程处理错误。执行的固件错误处理例程也会将错误信息记录到日志中。系统和方法提供协调的错误处理，增强错误恢复，提供错误控制和维护系统可用性。

7. 发明授权

US07308610B2 Method and apparatus for handling errors in a processing system 失效
标题翻译：用于处理处理系统中的错误的方法和装置
公开(公告)号：US07308610B2
公开(公告)日：2007-12-11
申请号：US11009166
申请日：2004-12-10
申请人： Rajendra Kuramkote , Suresh Marisetty , Koichi Yamada , Scott Brenden , William Cheung
发明人： Rajendra Kuramkote , Suresh Marisetty , Koichi Yamada , Scott Brenden , William Cheung
IPC分类号： G06F11/00
CPC分类号： G06F11/366 , G06F11/0793
摘要： A processing system may include an operating system (OS) and one or more specialized error handling modules to be registered with the OS after the processing system is powered on. The OS may also include a master policy module. The specialized error handling module may collect error data from a component of the processing system, and may generate abstracted error data, based at least in part on the collected error data. The master policy module may determine a recovery action to be taken, based at least in part on the abstracted error data. The OS may also include an error collection routine that calls one or more specialized error handling modules in response to detecting a hardware error. The error collection routine may also retrieve information from firmware in response to detecting the hardware error. Other embodiments are described and claimed.
摘要翻译：处理系统可以包括操作系统（OS）和一个或多个在处理系统通电之后向OS注册的专门的错误处理模块。操作系统还可以包括主策略模块。专门的错误处理模块可以从处理系统的组件收集错误数据，并且可以至少部分地基于所收集的错误数据来生成抽象的错误数据。主策略模块可以至少部分地基于抽象的错误数据来确定要采取的恢复动作。 OS还可以包括响应于检测到硬件错误而调用一个或多个专门的错误处理模块的错误收集例程。响应于检测到硬件错误，错误收集例程还可以从固件检索信息。描述和要求保护其他实施例。

8. 发明授权

US07721148B2 Method and apparatus for redirection of machine check interrupts in multithreaded systems 有权
标题翻译：多线程系统中机器检查中断重定向的方法和装置
公开(公告)号：US07721148B2
公开(公告)日：2010-05-18
申请号：US11478797
申请日：2006-06-29
申请人： Scott Brenden , Suresh Marisetty , Kushagra Vaid
发明人： Scott Brenden , Suresh Marisetty , Kushagra Vaid
IPC分类号： G06F13/24
CPC分类号： G06F11/0793 , G06F11/0715 , G06F11/0724
摘要： Disclosed is a communication mechanism among hardware, firmware and system software in order to redirect interrupts or other hardware events to only one thread execution context of an error domain for a multi-threaded processing system. Other embodiments are also described and claimed.
摘要翻译：公开了硬件，固件和系统软件之间的通信机制，以便将中断或其他硬件事件重定向到用于多线程处理系统的错误域的仅一个线程执行上下文。还描述和要求保护其他实施例。

9. 发明申请

US20080005615A1 Method and apparatus for redirection of machine check interrupts in multithreaded systems 有权
标题翻译：多线程系统中机器检查中断重定向的方法和装置
公开(公告)号：US20080005615A1
公开(公告)日：2008-01-03
申请号：US11478797
申请日：2006-06-29
申请人： Scott Brenden , Suresh Marisetty , Kushagra Vaid
发明人： Scott Brenden , Suresh Marisetty , Kushagra Vaid
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0715 , G06F11/0724
摘要： Disclosed is a communication mechanism among hardware, firmware and system software in order to redirect interrupts or other hardware events to only one thread execution context of an error domain for a multi-threaded processing system. Other embodiments are also described and claimed.
摘要翻译：公开了硬件，固件和系统软件之间的通信机制，以便将中断或其他硬件事件重定向到用于多线程处理系统的错误域的仅一个线程执行上下文。还描述和要求保护其他实施例。

10. 发明申请

US20070220332A1 Configurable error handling apparatus and methods to operate the same 有权
标题翻译：可配置的错误处理设备和操作方法
公开(公告)号：US20070220332A1
公开(公告)日：2007-09-20
申请号：US11352961
申请日：2006-02-13
申请人： Suresh Marisetty , Baskaran Ganesan , Gautam Doshi , Murugasamy Nachimuthu , Koichi Yamada , Jose Vargas , Jim Crossland , Stan Domen
发明人： Suresh Marisetty , Baskaran Ganesan , Gautam Doshi , Murugasamy Nachimuthu , Koichi Yamada , Jose Vargas , Jim Crossland , Stan Domen
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0781
摘要： Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.
摘要翻译：公开了可配置的误差处理装置及其操作方法。示例性设备包括半导体封装中的处理器核心，半导体封装中的硬件功能块，半导体封装中的错误处理器，其中错误处理程序可配置为将错误数据从硬件功能块路由到至少一个第一错误日志或第二错误日志，并将来自硬件功能块的错误信号路由到操作系统或固件中的至少一个，并且其中处理器核心配置错误处理程序和硬件功能块。

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