专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09306041B2 Vertical type semiconductor devices 有权
标题翻译：垂直型半导体器件
公开(公告)号：US09306041B2
公开(公告)日：2016-04-05
申请号：US14156607
申请日：2014-01-16
申请人： Sung-Min Hwang , Han-Soo Kim , Woon-Kyung Lee , Won-Seok Cho
发明人： Sung-Min Hwang , Han-Soo Kim , Woon-Kyung Lee , Won-Seok Cho
IPC分类号： H01L29/66 , H01L29/792 , H01L27/115
CPC分类号： H01L29/66833 , H01L27/11575 , H01L27/11582 , H01L29/7926
摘要： A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.
摘要翻译：垂直型半导体器件包括包括第一和第二字线的第一和第二字线结构。字线围绕多个柱结构，其被提供以将字线连接到相应的字符串选择线。连接图案将相邻的第一和第二字线的对电连接在同一平面中。该设备可以是非易失性存储设备或不同类型的设备。

2. 发明授权

US09087861B2 Methods of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09087861B2
公开(公告)日：2015-07-21
申请号：US14156781
申请日：2014-01-16
申请人： Sung-Min Hwang , Han-Soo Kim , Woon-Kyung Lee , Won-Seok Cho
发明人： Sung-Min Hwang , Han-Soo Kim , Woon-Kyung Lee , Won-Seok Cho
IPC分类号： H01L21/336 , H01L29/66 , H01L29/792 , H01L27/115
CPC分类号： H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.
摘要翻译：制造垂直型存储装置的方法包括在基板上堆叠第一下绝缘层，一层下牺牲层和第二下绝缘层，通过堆叠牺牲层和绝缘层形成堆叠结构，并蚀刻边缘部分堆叠结构以形成初步的阶梯状图案结构。初步阶形形状图案结构具有阶梯形边缘部分。形成与基板表面接触的柱结构。部分地蚀刻初步阶形状图案结构，下牺牲层和第一下绝缘层和第二下绝缘层，以形成第一开口部分和第二开口部分，以形成台阶状图形结构。第二开口部分切割下牺牲层的至少边缘部分。

3. 发明授权

US08563378B2 Manufacturing semiconductor devices 有权
标题翻译：制造半导体器件
公开(公告)号：US08563378B2
公开(公告)日：2013-10-22
申请号：US13238104
申请日：2011-09-21
申请人： Jae-Joo Shim , Han-Soo Kim , Won-Seok Cho , Jae-Hoon Jang , Sang-Yong Park
发明人： Jae-Joo Shim , Han-Soo Kim , Won-Seok Cho , Jae-Hoon Jang , Sang-Yong Park
IPC分类号： H01L21/336
CPC分类号： H01L29/7831 , H01L27/11582 , H01L29/7926
摘要： A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.
摘要翻译：半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层之上，在最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。

4. 发明申请

US20110287590A1 CONTACT STRUCTURES IN SUBSTRATE HAVING BONDED INTERFACE, SEMICONDUCTOR DEVICE INCLUDING THE SAME, METHODS OF FABRICATING THE SAME 失效
标题翻译：具有接合界面的基板中的接触结构，包括其的半导体器件，其制造方法
公开(公告)号：US20110287590A1
公开(公告)日：2011-11-24
申请号：US13204385
申请日：2011-08-05
申请人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk KIm , Young-Chul Jang
发明人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk KIm , Young-Chul Jang
IPC分类号： H01L21/768
CPC分类号： H01L27/11519 , G11C5/02 , G11C16/0483 , H01L21/76898 , H01L23/481 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/11578 , H01L2924/0002 , H01L2924/00
摘要： On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.
摘要翻译：接触结构的实施例可以包括在下基板上的下绝缘层，下绝缘层上的上基板，穿过上基板以延伸到下绝缘层中的沟槽，在上基板和下绝缘层，槽中的上绝缘层和穿过槽中的上绝缘层的接触插塞延伸到下绝缘层中。

5. 发明授权

US08343812B2 Contact structures in substrate having bonded interface, semiconductor device including the same, methods of fabricating the same 失效
标题翻译：具有接合界面的基板中的接触结构，包括该接合界面的半导体器件，其制造方法
公开(公告)号：US08343812B2
公开(公告)日：2013-01-01
申请号：US13204385
申请日：2011-08-05
申请人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk Kim , Young-Chul Jang
发明人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk Kim , Young-Chul Jang
IPC分类号： H01L21/82
CPC分类号： H01L27/11519 , G11C5/02 , G11C16/0483 , H01L21/76898 , H01L23/481 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/11578 , H01L2924/0002 , H01L2924/00
摘要： On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.
摘要翻译：接触结构的实施例可以包括在下基板上的下绝缘层，下绝缘层上的上基板，穿过上基板以延伸到下绝缘层中的沟槽，在上基板和下绝缘层，槽中的上绝缘层和穿过槽中的上绝缘层的接触插塞延伸到下绝缘层中。

6. 发明申请

US20100012980A1 Contact Structures in Substrate Having Bonded Interface, Semiconductor Device Including the Same, Methods of Fabricating the Same 审中-公开
标题翻译：具有接合界面的基板中的接触结构，包括其的半导体器件，其制造方法
公开(公告)号：US20100012980A1
公开(公告)日：2010-01-21
申请号：US12504989
申请日：2009-07-17
申请人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk Kim , Young-Chul Jang
发明人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk Kim , Young-Chul Jang
IPC分类号： H01L29/68 , H01L23/52 , H01L21/768
CPC分类号： H01L27/11519 , G11C5/02 , G11C16/0483 , H01L21/76898 , H01L23/481 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/11578 , H01L2924/0002 , H01L2924/00
摘要： On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.
摘要翻译：接触结构的实施例可以包括在下基板上的下绝缘层，下绝缘层上的上基板，穿过上基板以延伸到下绝缘层中的沟槽，在上基板和下绝缘层，槽中的上绝缘层和穿过槽中的上绝缘层的接触插塞延伸到下绝缘层中。

7. 发明申请

US20120009767A1 METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING METALLIZATION COMPRISING SELECT LINES, BIT LINES AND WORD LINES 有权
标题翻译：形成包含选择线，位线和字线的金属化的半导体器件的方法
公开(公告)号：US20120009767A1
公开(公告)日：2012-01-12
申请号：US13236000
申请日：2011-09-19
申请人： Young-Chul JANG , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Yang-Soo Son , Min-Sung Song
发明人： Young-Chul JANG , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Yang-Soo Son , Min-Sung Song
IPC分类号： H01L21/20
CPC分类号： H01L27/0688 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.
摘要翻译：半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层在第二保护层和第二区域的第一绝缘层上。

8. 发明申请

US20100275842A1 Evaporating apparatus 有权
标题翻译：蒸发装置
公开(公告)号：US20100275842A1
公开(公告)日：2010-11-04
申请号：US12659987
申请日：2010-03-26
申请人： Jae-Wan Park , You-Min Cha , Jae-Hong Ahn , Won-Seok Cho , Jae-Mork Park , Min-Jeong Hwang
发明人： Jae-Wan Park , You-Min Cha , Jae-Hong Ahn , Won-Seok Cho , Jae-Mork Park , Min-Jeong Hwang
IPC分类号： C23C16/00
CPC分类号： C23C14/243 , C23C14/044
摘要： Provided is an evaporating apparatus that deposits a deposition material onto a treatment object. The evaporating apparatus includes a base, a deposition source, and first and second correction units. The deposition source deposits the deposition material onto the treatment object. The base is disposed separately from the treatment object. The deposition source is placed on a surface of the base. The first and second correction units located between the deposition source and the treatment object. The first and second correction units are disposed on outer regions of the deposition source and face each other. Each of the first and second correction units rotates to control the thickness of a layer formed by the deposition material deposited on the treatment object.
摘要翻译：提供了一种将沉积材料沉积到处理物体上的蒸发装置。蒸发装置包括基座，沉积源以及第一和第二校正单元。沉积源将沉积材料沉积到处理对象上。基座与治疗对象分开设置。沉积源放置在基底的表面上。位于沉积源和处理对象之间的第一和第二校正单元。第一和第二校正单元设置在沉积源的外部区域上并且彼此面对。第一和第二校正单元中的每一个旋转以控制由沉积在处理对象上的沉积材料形成的层的厚度。

9. 发明申请

US20090233405A1 METHODS OF FORMING NAND-TYPE NONVOLATILE MEMORY DEVICES 有权
标题翻译：形成NAND型非易失性存储器件的方法
公开(公告)号：US20090233405A1
公开(公告)日：2009-09-17
申请号：US12474896
申请日：2009-05-29
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.
摘要翻译：形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层半导体衬底的整个表面使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

10. 发明授权

US07554140B2 Nand-type non-volatile memory device 失效
标题翻译： Nand型非易失性存储器件
公开(公告)号：US07554140B2
公开(公告)日：2009-06-30
申请号：US11651892
申请日：2007-01-10
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L31/062
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.
摘要翻译：提供了一种NAND型非易失性存储器件及其形成方法。在该方法中，多个单元层层叠在半导体基板上。用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式