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1. 发明申请

US20130308401A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20130308401A1
公开(公告)日：2013-11-21
申请号：US13615371
申请日：2012-09-13
申请人： Sun Suk YANG
发明人： Sun Suk YANG
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C29/06
摘要： A semiconductor memory device includes an internal signal generation block configured to generate a control signal which is enabled from a generation time of an internal active signal enabled if it is determined that a combination of external commands in synchronization with a rising edge of an external clock inputted from an outside is a preset combination, to a disable time an internal idle signal; and an internal command signal generation block configured to generate an internal write signal if it is determined that a combination of counting signals counted during an enable period of the control signal is a first combination and generate an internal precharge signal if it is determined that the combination of the counting signals is a second combination.
摘要翻译：半导体存储器件包括内部信号产生模块，其被配置为：如果确定与输入的外部时钟的上升沿同步的外部命令的组合，则产生可从内部有效信号的生成时间使能的控制信号从外部是预设组合，禁用时间内部空闲信号; 以及内部命令信号生成块，其被配置为如果确定在所述控制信号的使能周期期间计数的计数信号的组合是第一组合并且如果确定所述组合则生成内部预充电信号，则生成内部写入信号的计数信号是第二组合。

2. 发明申请

US20120026809A1 MULTI-BIT TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器的多位测试电路
公开(公告)号：US20120026809A1
公开(公告)日：2012-02-02
申请号：US12966650
申请日：2010-12-13
申请人： Sun Suk YANG
发明人： Sun Suk YANG
IPC分类号： G11C29/00 , G11C7/22
CPC分类号： G11C29/28
摘要： A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode.
摘要翻译：用于半导体存储器的多位测试电路被配置为使得有效命令激活有效信号。在多位测试模式下，以不同的定时将至少两个有效信号分别输入到多个存储体。

3. 发明申请

US20070291576A1 ADDRESS LATCH CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件的地址锁存电路
公开(公告)号：US20070291576A1
公开(公告)日：2007-12-20
申请号：US11683532
申请日：2007-03-08
申请人： Sun Suk YANG
发明人： Sun Suk YANG
IPC分类号： G11C8/18
CPC分类号： G11C8/06 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C2207/107
摘要： An address latch circuit of a semiconductor memory device is provided. The address latch circuit includes a first address latch part, which latches a first address signal fed from outside according to a first address latch signal and outputs a second address signal. An address shift part shifts the second address signal according to a divided clock, which is divided from an external clock, and a write latency signal, and outputs a third address signal. A second address latch part latches the third address signal according to a second address latch signal and outputs a fourth address signal.
摘要翻译：提供半导体存储器件的地址锁存电路。地址锁存电路包括第一地址锁存部分，其根据第一地址锁存信号锁存从外部馈送的第一地址信号，并输出第二地址信号。地址移位部分根据从外部时钟划分的分频时钟和写等待时间信号来移位第二地址信号，并输出第三地址信号。第二地址锁存部分根据第二地址锁存信号锁存第三地址信号，并输出第四地址信号。

4. 发明申请

US20100214865A1 SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储装置及其控制方法
公开(公告)号：US20100214865A1
公开(公告)日：2010-08-26
申请号：US12650412
申请日：2009-12-30
申请人： Sun Suk YANG
发明人： Sun Suk YANG
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： A semiconductor memory apparatus includes: an address buffer configured to buffer an input address and generate a buffered address; a command buffer configured to buffer a chip selection command and generate a buffered command; a latch control unit configured to receive an internal clock and the buffered command and generate a latch control signal; and an address latch unit configured to latch the buffered address based on the latch control signal.
摘要翻译：半导体存储装置包括：地址缓冲器，被配置为缓冲输入地址并生成缓冲地址; 配置为缓冲芯片选择命令并生成缓冲命令的命令缓冲器; 闩锁控制单元，被配置为接收内部时钟和缓冲命令并产生锁存控制信号; 以及地址锁存单元，被配置为基于所述锁存控制信号来锁存缓冲的地址。

5. 发明申请

US20080157845A1 CLOCK BUFFER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING AN INPUT THEREOF 审中-公开
标题翻译：时钟缓冲器电路，半导体存储器件及其输入控制方法
公开(公告)号：US20080157845A1
公开(公告)日：2008-07-03
申请号：US11776327
申请日：2007-07-11
申请人： Sun Suk YANG
发明人： Sun Suk YANG
IPC分类号： G11C8/02 , G06F1/04
CPC分类号： G11C8/18 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C7/225
摘要： The present invention relates to a semiconductor memory device having a clock buffer circuit which buffers an external clock to generate an internal clock, wherein the clock buffer circuit comprises a rising clock buffer which buffers an external clock to generate a rising internal clock corresponding to a rising edge of the external clock; and a falling clock buffer which buffers the external clock to generate a falling internal clock corresponding to a falling edge of the external clock, whereby the external signal is input to the internal circuit in synchronization with the rising internal clock and the falling internal clock.
摘要翻译：本发明涉及具有时钟缓冲电路的半导体存储器件，其缓冲外部时钟以产生内部时钟，其中时钟缓冲电路包括一个上升时钟缓冲器，其缓冲外部时钟以产生对应于上升沿的上升内部时钟外部时钟的边缘; 以及下降时钟缓冲器，其缓冲外部时钟以产生对应于外部时钟的下降沿的下降的内部时钟，由此外部信号与内部时钟和下降的内部时钟同步地输入到内部电路。

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