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1. 发明授权

US07639056B2 Ultra low area overhead retention flip-flop for power-down applications 有权
标题翻译：用于断电应用的超低面积开销保持触发器
公开(公告)号：US07639056B2
公开(公告)日：2009-12-29
申请号：US11138788
申请日：2005-05-26
申请人： Sumanth Katte Gururajarao , Hugh T. Mair , David B. Scott , Uming Ko
发明人： Sumanth Katte Gururajarao , Hugh T. Mair , David B. Scott , Uming Ko
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356008 , H04W52/0283 , Y02D70/122
摘要： In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.
摘要翻译：在用于数据保持的方法和系统中，数据输入由第一锁存器锁存。耦合到第一锁存器的第二锁存器接收用于保持的数据输入，而在备用电源模式下第一锁存器不工作。第一个锁存器在待机电源模式期间从关闭的第一电源线接收电力。第二锁存器从第二电源线接收电力。控制器接收时钟输入和保持信号，并向第一锁存器和第二锁存器提供时钟输出。保持信号的改变表示转变到待机功率模式。控制器继续将时钟输出保持在预定的电压电平，并且第二锁存器在待机功率模式下继续从第二电源线接收电力，从而保留数据输入。

2. 发明授权

US10275010B2 Fast and Autonomous mechanism for CPU OC protection 有权
公开(公告)号：US10275010B2
公开(公告)日：2019-04-30
申请号：US15119731
申请日：2015-02-16
申请人： MediaTek Singapore Pte. Ltd. , Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
发明人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
IPC分类号： G06F1/32 , G06F1/324 , G06F1/28 , G06F1/3206 , G06F1/3296
摘要： A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.

3. 发明申请

US20170068296A1 Fast and Autonomous Mechanism for CPU OC Protection 审中-公开
标题翻译：快速自主的CPU OC保护机制
公开(公告)号：US20170068296A1
公开(公告)日：2017-03-09
申请号：US15119731
申请日：2015-02-16
申请人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist , MediaTek Singapore Pte. Ltd.
发明人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/28 , G06F1/3206 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.
摘要翻译：提供了一种检测和防止过电流引起的系统故障的方法。 OC保护控制器根据接收到的CPU活动信息监视CPU总功耗。响应监视，如果CPU功耗超过阈值，则OC保护控制器输出频率抖动控制信号，以降低CPU时钟频率，使CPU不达到OC限制。 OC保护控制器还输出PLL频率控制信号，以减少PLL时钟频率，提高系统效率。

4. 发明授权

US06989702B2 Retention register with normal functionality independent of retention power supply 有权
标题翻译：保持寄存器具有正常功能，独立于保持电源
公开(公告)号：US06989702B2
公开(公告)日：2006-01-24
申请号：US10613271
申请日：2003-07-03
申请人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh T. Mair , Peter H. Cumming , Franck Dahan
发明人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh T. Mair , Peter H. Cumming , Franck Dahan
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356008 , G11C14/00
摘要： State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1–M3; M1–M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to anode (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.
摘要翻译：提供了用于数字IC操作的低功率待机模式的状态保持寄存器，其中：差分电路（M 1 -M 3; M 1 -M 4）用于从常规功能锁存器加载阴影锁存器; 用于将数据从阴影锁存器恢复到正常功能锁存器的信号（REST，RESTZ）是“无关”信号，而阴影锁存器在低功耗待机模式期间保留数据; 来自阴影锁存器的保留数据经由连接到提供保留数据的阴影锁存器的阳极（N10）的晶体管栅极恢复到正常功能锁存器; 除了阴影锁存器电源（VRETAIN）之外的电源（VDD）为数据恢复操作供电; 并且正常功能锁存器可独立于高V 1晶体管（M 1，M 2，M 5和M 6; M 3，M 4，M 5和M 6）的工作状态工作，用于实现状态保留功能。此外，提供隔离装置以在逻辑模块断电时保持逻辑模块的输出。

5. 发明授权

US07282905B2 System and method for IDDQ measurement in system on a chip (SOC) design 有权
标题翻译：系统芯片（SOC）设计中IDDQ测量的系统和方法
公开(公告)号：US07282905B2
公开(公告)日：2007-10-16
申请号：US11010135
申请日：2004-12-10
申请人： Wei Chen , Hugh T. Mair , Uming Ko , David B. Scott
发明人： Wei Chen , Hugh T. Mair , Uming Ko , David B. Scott
IPC分类号： G01R31/26
CPC分类号： G01R31/3008 , G01R31/3012
摘要： System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for an integrated circuit made up of a plurality of main switches (such as main switch 410) selectively coupling a power sub-domain to a power source pin, a plurality of pi-switches (such as pi-switch 415) selectively coupling pairs of power sub-domains, and a plurality of IDDQ switches (such as IDDQ switch 425) selectively coupling the power sub-domains to a VIDDQ pin. The pi-switches can decouple the power sub-domains while the IDDQ switches can enable the measurement of the quiescent current in the power sub-domains. The use of pi-switches and IDDQ switches can permit the measurement of the quiescent current in the power sub-domains without requiring the use of isolation buffers and needed to powering on and off the integrated circuit between current measurements in the different power sub-domains.
摘要翻译：通过测量IDDQ来检测大型集成电路中的晶体管故障的系统和方法。优选实施例包括由多个选择性地将电源子域耦合到电源引脚的多个主开关（例如主开关410）构成的集成电路的开关结构，多个pi开关（例如，开关415）选择性地耦合功率子域对，以及选择性地将功率子域耦合到VIDDQ引脚的多个IDDQ开关（例如IDDQ开关425）。 pi开关可以对功率子域进行去耦，而IDDQ开关可以测量电源子域中的静态电流。 pi开关和IDDQ开关的使用可以允许测量电源子域中的静态电流，而不需要使用隔离缓冲器，并且需要在不同功率子域中的电流测量之间为集成电路供电和关断。

6. 发明申请

US20100103760A1 Memory Power Management Systems and Methods 有权
标题翻译：内存电源管理系统和方法
公开(公告)号：US20100103760A1
公开(公告)日：2010-04-29
申请号：US12258747
申请日：2008-10-27
申请人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
发明人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C5/147
摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
摘要翻译：提供了内存电源管理系统和方法。本发明的一个实施例包括存储器电源管理系统。该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

7. 发明授权

US07920020B2 System and method for auto-power gating synthesis for active leakage reduction 有权
标题翻译：用于自动电源门控合成的系统和方法，用于主动泄漏减少
公开(公告)号：US07920020B2
公开(公告)日：2011-04-05
申请号：US12814195
申请日：2010-06-11
申请人： Alice Wang , Hugh T. Mair , Gordon Gammie , Uming Ko
发明人： Alice Wang , Hugh T. Mair , Gordon Gammie , Uming Ko
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.
摘要翻译：一种方法包括解析集成电路的设计以在自动功率选通电源域中定义单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线生成集成电路的布局。解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。

8. 发明授权

US07760011B2 System and method for auto-power gating synthesis for active leakage reduction 有权
标题翻译：用于自动电源门控合成的系统和方法，用于主动泄漏减少
公开(公告)号：US07760011B2
公开(公告)日：2010-07-20
申请号：US11947012
申请日：2007-11-29
申请人： Alice Wang , Hugh T. Mair , Gordon Gammie , Uming Ko
发明人： Alice Wang , Hugh T. Mair , Gordon Gammie , Uming Ko
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.
摘要翻译：一种方法包括解析集成电路的设计以在自动功率选通电源域中定义单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线生成集成电路的布局。解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。

9. 发明申请

US20110216619A1 MEMORY POWER MANAGEMENT SYSTEMS AND METHODS 审中-公开
标题翻译：存储电源管理系统和方法
公开(公告)号：US20110216619A1
公开(公告)日：2011-09-08
申请号：US13106612
申请日：2011-05-12
申请人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
发明人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
摘要翻译：提供了内存电源管理系统和方法。本发明的一个实施例包括存储器电源管理系统。该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

10. 发明授权

US07570100B2 Potential and rate adjust header switch circuitry reducing transient current 有权
标题翻译：电位和速率调节头开关电路减少瞬态电流
公开(公告)号：US07570100B2
公开(公告)日：2009-08-04
申请号：US10918869
申请日：2004-08-16
申请人： Wei Dong , Hiep Tran , Hugh T. Mair , Uming Ko
发明人： Wei Dong , Hiep Tran , Hugh T. Mair , Uming Ko
IPC分类号： H03K17/687
CPC分类号： H03K19/00346 , H03K17/166 , H03K17/167 , H03K17/687 , H03K19/0016
摘要： System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as switch arrangement 400) with a plurality of switches (such as switch 405) coupling a power supply to the circuitry. Each switch is individually controlled by a control signal and is turned on sequentially. Also coupled to each switch is a pre-driver circuit (such as pre-driver circuit 410). The pre-driver circuit comprises a potential adjust circuit (such as potential adjust circuit 505) that rapidly adjusts a voltage potential at the switch and a rate adjust circuit (such as the rate adjust circuit 520) that accelerates the power ramp-up across the switch once transient currents are no longer a concern. Adjusting the voltage potential so that the switch operates in a saturation mode increases an effective capacitance across the switch and thereby retarding the power ramp-up across the switch.
摘要翻译：为电路提供电源同时避免大的瞬态电流的系统和方法。优选实施例包括具有将电源耦合到电路的多个开关（例如开关405）的分布式开关（例如开关装置400）。每个开关由控制信号单独控制，并依次打开。还耦合到每个开关是预驱动器电路（例如预驱动器电路410）。预驱动电路包括一个电位调节电路（例如电位调节电路505），其快速地调节开关处的电压电位;以及速率调节电路（例如速率调整电路520），其加速横跨一旦瞬态电流不再需要切换，调整电压电位以使开关工作在饱和模式，从而增加开关两端的有效电容，从而延迟开关上的功率上升。

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