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1. 发明申请

US20080067581A1 Non-volatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080067581A1
公开(公告)日：2008-03-20
申请号：US11896834
申请日：2007-09-06
申请人： Sug-Hun Hong , Myoung-Bum Lee , Gab-Jin Nam
发明人： Sug-Hun Hong , Myoung-Bum Lee , Gab-Jin Nam
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory device includes a tunnel insulating layer pattern on a channel region of a substrate, a charge trapping layer pattern on the tunnel insulating layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode including a conductive layer pattern on the blocking layer pattern and a barrier layer pattern on the conductive layer pattern. The conductive layer pattern includes a metal
摘要翻译：非易失性存储器件包括在衬底的通道区域上的隧道绝缘层图案，隧道绝缘层图案上的电荷俘获层图案，电荷俘获层图案上的阻挡层图案，以及包括导电阻挡层图案上的层图案和导电层图案上的阻挡层图案。导电层图案包括金属

2. 发明授权

US07696563B2 Non-volatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07696563B2
公开(公告)日：2010-04-13
申请号：US11896834
申请日：2007-09-06
申请人： Sug-Hun Hong , Myoung-Bum Lee , Gab-Jin Nam
发明人： Sug-Hun Hong , Myoung-Bum Lee , Gab-Jin Nam
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory device includes a tunnel insulating layer pattern on a channel region of a substrate, a charge trapping layer pattern on the tunnel insulating layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode including a conductive layer pattern on the blocking layer pattern and a barrier layer pattern on the conductive layer pattern. The conductive layer pattern includes a metal.
摘要翻译：非易失性存储器件包括在衬底的通道区域上的隧道绝缘层图案，隧道绝缘层图案上的电荷俘获层图案，电荷俘获层图案上的阻挡层图案，以及包括导电阻挡层图案上的层图案和导电层图案上的阻挡层图案。导电层图案包括金属。

3. 发明授权

US07646067B2 Complementary metal-oxide-semiconductor transistor including multiple gate conductive layers and method of manufacturing the same 失效
标题翻译：包括多个栅极导电层的互补金属氧化物半导体晶体管及其制造方法
公开(公告)号：US07646067B2
公开(公告)日：2010-01-12
申请号：US11891337
申请日：2007-08-10
申请人： Gab-Jin Nam , Myoung-Bum Lee
发明人： Gab-Jin Nam , Myoung-Bum Lee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L23/62
CPC分类号： H01L21/823842 , Y10S257/914
摘要： A CMOS transistor and a method of manufacturing the CMOS transistor are disclosed. An NMOS transistor is formed on a first region of a semiconductor substrate. A PMOS transistor is formed on a second region of a semiconductor substrate. The NMOS transistor includes a first gate conductive layer. The PMOS transistor includes a second gate conductive layer. The first gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.0 eV to about 4.3 eV. The third gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.7 eV to about 5.0 eV.
摘要翻译：公开了CMOS晶体管和制造CMOS晶体管的方法。 NMOS晶体管形成在半导体衬底的第一区域上。 PMOS晶体管形成在半导体衬底的第二区域上。 NMOS晶体管包括第一栅极导电层。 PMOS晶体管包括第二栅极导电层。第一栅极导电层包括在从下部朝向上部的方向上氮浓度增加的金属。此外，金属具有约4.0eV至约4.3eV的功函数。第三栅极导电层包括在从下部朝向上部的方向上氮浓度增加的金属。此外，金属具有约4.7eV至约5.0eV的功函数。

4. 发明申请

US20080042213A1 Complementary metal-oxide-semiconductor transistor and method of manufacturing the same 失效
标题翻译：互补金属氧化物半导体晶体管及其制造方法
公开(公告)号：US20080042213A1
公开(公告)日：2008-02-21
申请号：US11891337
申请日：2007-08-10
申请人： Gab-Jin Nam , Myoung-Bum Lee
发明人： Gab-Jin Nam , Myoung-Bum Lee
IPC分类号： H01L21/8238 , H01L29/94
CPC分类号： H01L21/823842 , Y10S257/914
摘要： A CMOS transistor and a method of manufacturing the CMOS transistor are disclosed. An NMOS transistor is formed on a first region of a semiconductor substrate. A PMOS transistor is formed on a second region of a semiconductor substrate. The NMOS transistor includes a first gate conductive layer. The PMOS transistor includes a second gate conductive layer. The first gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.0 eV to about 4.3 eV. The third gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.7 eV to about 5.0 eV.
摘要翻译：公开了CMOS晶体管和制造CMOS晶体管的方法。 NMOS晶体管形成在半导体衬底的第一区域上。 PMOS晶体管形成在半导体衬底的第二区域上。 NMOS晶体管包括第一栅极导电层。 PMOS晶体管包括第二栅极导电层。第一栅极导电层包括在从下部朝向上部的方向上氮浓度增加的金属。此外，金属具有约4.0eV至约4.3eV的功函数。第三栅极导电层包括在从下部朝向上部的方向上氮浓度增加的金属。此外，金属具有约4.7eV至约5.0eV的功函数。

5. 发明授权

US07585756B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07585756B2
公开(公告)日：2009-09-08
申请号：US11839387
申请日：2007-08-15
申请人： Gab-Jin Nam , Myoung-Bum Lee
发明人： Gab-Jin Nam , Myoung-Bum Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/78
摘要： A MOS transistor includes a substrate, source/drain regions formed at portions of the substrate, and a channel region formed between the source/drain regions. The MOS transistor further includes a gate structure having a gate insulation layer pattern and a gate electrode formed on the channel region. The gate electrode includes a first gate conductive layer pattern and a second gate conductive layer pattern. The first gate conductive layer pattern has a nitrogen concentration gradient gradually increasing from a lower portion of the first gate conductive layer pattern to an upper portion of the first gate conductive layer pattern. The second gate conductive layer pattern includes a material having a resistance substantially lower than a resistance of the first gate conductive layer pattern.
摘要翻译： MOS晶体管包括衬底，形成在衬底的部分处的源极/漏极区域和形成在源极/漏极区域之间的沟道区域。 MOS晶体管还包括具有栅极绝缘层图案的栅极结构和形成在沟道区上的栅电极。栅电极包括第一栅极导电层图案和第二栅极导电层图案。第一栅极导电层图案具有从第一栅极导电层图案的下部逐渐增加到第一栅极导电层图案的上部的氮浓度梯度。第二栅极导电层图案包括具有基本上低于第一栅极导电层图案的电阻的电阻的材料。

6. 发明申请

US20140070300A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20140070300A1
公开(公告)日：2014-03-13
申请号：US13724187
申请日：2012-12-21
申请人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
发明人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.
摘要翻译：半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体层在垂直方向。这些部分中的至少一些是相邻的多个通道的相应通道。每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极或填充层图案。

7. 发明申请

US20110303970A1 VERTICAL SEMICONDUCTOR DEVICES 有权
标题翻译：垂直半导体器件
公开(公告)号：US20110303970A1
公开(公告)日：2011-12-15
申请号：US13104377
申请日：2011-05-10
申请人： Jin-Gyun Kim , Myoung-Bum Lee
发明人： Jin-Gyun Kim , Myoung-Bum Lee
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A vertical semiconductor device and a method of making a vertical semiconductor device include a first semiconductor pattern formed on a substrate and a first gate structure formed on a sidewall of the first semiconductor pattern. A second semiconductor pattern is formed on the first semiconductor pattern. A plurality of insulating interlayer patterns is formed on sidewalls of the second semiconductor pattern. The insulating interlayer patterns are spaced apart from each other to define grooves between the insulating interlayer patterns. The plurality of second gate structures is disposed in the grooves, respectively.
摘要翻译：垂直半导体器件和制造垂直半导体器件的方法包括形成在衬底上的第一半导体图案和形成在第一半导体图案的侧壁上的第一栅极结构。在第一半导体图案上形成第二半导体图案。在第二半导体图案的侧壁上形成多个绝缘层间图案。绝缘层间图案彼此间隔开以限定绝缘层间图案之间的凹槽。多个第二栅极结构分别设置在槽中。

8. 发明申请

US20110237055A1 Methods of Manufacturing Stacked Semiconductor Devices 审中-公开
标题翻译：堆叠半导体器件制造方法
公开(公告)号：US20110237055A1
公开(公告)日：2011-09-29
申请号：US13053291
申请日：2011-03-22
申请人： Yong-hoon Son , Si-Young Choi , Myoung-Bum Lee , Ki-Hyun Hwang , Seung-Jae Baik , Jeong Hee Han
发明人： Yong-hoon Son , Si-Young Choi , Myoung-Bum Lee , Ki-Hyun Hwang , Seung-Jae Baik , Jeong Hee Han
IPC分类号： H01L21/20
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11524 , H01L27/11551 , H01L27/1207
摘要： A stacked semiconductor device that is reliable by forming an insulating layer on a lower memory layer and by forming a single crystalline semiconductor in portions of the insulating layer. A method of manufacturing the stacked semiconductor device, including: providing a lower memory layer including a plurality of lower memory structures; forming an insulating layer on the lower memory layer; forming trenches by removing portions of the insulating layer; forming a preparatory semiconductor layer for filling the trenches; and forming a single crystalline semiconductor layer by phase-changing the preparatory semiconductor layer.
摘要翻译：通过在下部存储层上形成绝缘层，在绝缘层的一部分形成单晶半导体，可靠的叠层型半导体装置。一种制造叠层半导体器件的方法，包括：提供包括多个下部存储结构的下部存储层; 在下部存储层上形成绝缘层; 通过去除绝缘层的部分形成沟槽; 形成用于填充沟槽的准备半导体层; 以及通过相变所述预备半导体层来形成单晶半导体层。

9. 发明授权

US08916922B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US08916922B2
公开(公告)日：2014-12-23
申请号：US13724187
申请日：2012-12-21
申请人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
发明人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
IPC分类号： H01L29/792 , H01L27/115 , H01L29/66
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.
摘要翻译：半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体层在垂直方向。这些部分中的至少一些是相邻的多个通道的相应通道。每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极或填充层图案。

10. 发明授权

US06858529B2 Methods of forming contact plugs including polysilicon doped with an impurity having a lesser diffusion coefficient than phosphorus 有权
标题翻译：形成接触塞的方法，包括掺杂有比磷更小的扩散系数的杂质的多晶硅
公开(公告)号：US06858529B2
公开(公告)日：2005-02-22
申请号：US10440777
申请日：2003-05-19
申请人： Eun-Ae Chung , Myoung-Bum Lee , Young-Pil Kim , Jin-Gyun Kim , Bean-Jun Jin
发明人： Eun-Ae Chung , Myoung-Bum Lee , Young-Pil Kim , Jin-Gyun Kim , Bean-Jun Jin
IPC分类号： H01L21/28 , H01L21/225 , H01L21/285 , H01L21/768 , H01L23/485 , H01L21/4763
CPC分类号： H01L21/76877 , H01L21/2257 , H01L21/28525 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.
摘要翻译：形成半导体器件可以包括在包括其导电区域的半导体衬底上形成绝缘层，其中绝缘层具有暴露导电区域的一部分的接触孔。可以在接触孔中形成多晶硅接触插塞，其中多晶硅接触插塞的至少一部分掺杂有具有小于磷（P）的扩散系数的扩散系数的元件。还讨论了相关结构。

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