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1. 发明授权

US5499754A Fluxless soldering sample pretreating system 失效
标题翻译：无焊锡样品预处理系统
公开(公告)号：US5499754A
公开(公告)日：1996-03-19
申请号：US339770
申请日：1994-11-15
申请人： Stephen M. Bobbio , Nicholas G. Koopman , Sundeep Nangalia
发明人： Stephen M. Bobbio , Nicholas G. Koopman , Sundeep Nangalia
IPC分类号： B23K1/20 , B23K35/38 , H05K3/34 , C23F1/02 , B23K3/08
CPC分类号： B23K35/38 , B23K1/20 , B23K2201/36 , H05K3/3489
摘要： A fluxless soldering sample pretreating system includes a sample chamber having an opening therein and a sample holder. A sample chamber extension extends outwardly from the opening to define a passageway from the sample chamber extension, through the opening, and into the sample chamber. A fluorine-containing gas is supplied into the sample chamber extension. Am energy source such as a microwave oven surrounds the sample chamber extension. The microwave oven produces microwave energy in the sample chamber extension to form a plasma therein and dissociate the fluorine-containing gas into atomic fluorine. A perforated aluminum plate extends transversely across the passageway and blocks the plasma from traversing the passageway from the sample chamber extension into the sample chamber, while allowing the atomic fluorine to traverse the passageway from the sample chamber extension into the sample holder. A second chamber extension, gas supply and microwave oven may be added to improve uniformity for large samples.
摘要翻译：无助焊剂样品预处理系统包括其中具有开口的样品室和样品保持器。样品室延伸部从开口向外延伸以限定从样品室延伸部穿过开口并进入样品室的通道。向样品室延伸部供给含氟气体。诸如微波炉的能量源围绕样品室延伸。微波炉在样品室延伸部中产生微波能量，在其中形成等离子体，并将含氟气体解离为原子氟。穿孔铝板横向延伸穿过通道，并阻止等离子体横穿从样品室延伸部进入样品室的通道，同时允许原子氟穿过从样品室延伸部分进入样品架的通道。可以添加第二室延伸，气体供应和微波炉以改善大样品的均匀性。

2. 发明授权

US5407121A Fluxless soldering of copper 失效
标题翻译：铜的无焊焊接
公开(公告)号：US5407121A
公开(公告)日：1995-04-18
申请号：US155020
申请日：1993-11-19
申请人： Nicholas G. Koopman , Sundeep Nangalia
发明人： Nicholas G. Koopman , Sundeep Nangalia
IPC分类号： B23K1/20 , B23K35/38 , H05K3/34
CPC分类号： B23K35/38 , B23K1/20 , B23K2201/36 , H05K3/3489
摘要： A method of soldering a copper layer without the use of fluxing agents by exposing the copper layer to a fluorine-containing plasma. Solder is then placed onto the surface of the copper layer and reflowed. Reflow can take place at low temperatures, atmospheric pressure and in an inert or oxidizing atmosphere using standard solder reflow equipment.
摘要翻译：一种通过将铜层暴露于含氟等离子体而不使用助熔剂来焊接铜层的方法。然后将焊料放置在铜层的表面上并回流。回流可以使用标准的回流焊设备在低温，大气压和惰性或氧化性气氛中进行。

3. 发明授权

US5992729A Tacking processes and systems for soldering 失效
标题翻译：焊接工艺和系统
公开(公告)号：US5992729A
公开(公告)日：1999-11-30
申请号：US724910
申请日：1996-10-02
申请人： Nicholas G. Koopman , Sundeep Nangalia
发明人： Nicholas G. Koopman , Sundeep Nangalia
IPC分类号： B23K1/06 , H05K3/34 , B23K1/20 , B23K31/02
CPC分类号： B23K1/06 , H05K3/3436
摘要： A first component is soldered to a second component by placing the first component on the second component with solder therebetween, then ultrasonically vibrating at least one of the first and second components to thereby tack the solder to at least one of the first and second components, and by reflowing the solder. Ultrasonic vibration of at least one of the first and second components to thereby tack the solder is preferably performed for less than one second. A component placer places the first component on the second component with solder therebetween. An ultrasonic vibrator ultrasonically vibrates at least one of the placed first and second components, to thereby tack the solder to at least one of the placed first and second components. A solder reflower reflows the tacked solder to thereby solder the first component to the second component.
摘要翻译：将第一部件焊接到第二部件上，通过将第一部件放置在第二部件上，在其间具有焊料，然后对第一和第二部件中的至少一个进行超声波振动，从而将焊料固定到第一和第二部件中的至少一个，并通过回流焊料。第一和第二组分中的至少一个的超声波振动优选地进行少于1秒。组件放置器将第一部件放置在第二部件上，其间具有焊料。超声波振动器超声振动放置的第一和第二部件中的至少一个，从而将焊料固定到所放置的第一和第二部件中的至少一个。焊料回流焊机将固定的焊料回流，从而将第一部件焊接到第二部件。

4. 发明授权

US5251806A Method of forming dual height solder interconnections 失效
标题翻译：形成双高度焊料互连的方法
公开(公告)号：US5251806A
公开(公告)日：1993-10-12
申请号：US870647
申请日：1992-04-16
申请人： Birendra N. Agarwala , Aziz M. Ahsan , Arthur Bross , Mark F. Chadurjian , Nicholas G. Koopman , Li-Chung Lee , Karl J. Puttlitz , Sudipta K. Ray , James G. Ryan , Joseph G. Schaefer , Kamalesh K. Srivastava , Paul A. Totta , Erick G. Walton , Adolf E. Wirsing
发明人： Birendra N. Agarwala , Aziz M. Ahsan , Arthur Bross , Mark F. Chadurjian , Nicholas G. Koopman , Li-Chung Lee , Karl J. Puttlitz , Sudipta K. Ray , James G. Ryan , Joseph G. Schaefer , Kamalesh K. Srivastava , Paul A. Totta , Erick G. Walton , Adolf E. Wirsing
IPC分类号： H01L21/60 , H01L23/485 , H05K3/34 , H01L21/283
CPC分类号： H01L24/12 , H01L24/11 , H01L2224/11901 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/1357 , H01L2224/13582 , H01L2224/13583 , H01L2224/13647 , H01L2224/13655 , H01L2224/13657 , H01L2224/1366 , H01L2224/13664 , H01L2224/13666 , H01L2224/13669 , H01L2224/1367 , H01L2224/13671 , H01L2224/13672 , H01L2224/13676 , H01L2224/13679 , H01L2224/1368 , H01L2224/13681 , H01L2224/13684 , H01L24/16 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01046 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/15787 , H05K3/3431 , H05K3/3457
摘要： The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.
摘要翻译：本发明一般涉及新的互连及其制造方法，更具体地说，涉及一种细长的焊料互连及其制造方法。在电子载体上，形成焊盘，在其上沉积焊料块并用金属层封盖，从而形成细长的焊料互连。现在可以通过在已经被金属层覆盖的第一焊料块上形成第二焊料块来形成另外细长的焊料互连。可以通过用金属覆盖层封盖前述焊料块和/或最后的焊料块来形成附加的细长焊料互连。或者，封装层可以是形成在焊料块的侧壁上的侧壁间隔物的形式。

5. 发明授权

US5130779A Solder mass having conductive encapsulating arrangement 失效
标题翻译：具有导电包装安排的焊接质量
公开(公告)号：US5130779A
公开(公告)日：1992-07-14
申请号：US540256
申请日：1990-06-19
申请人： Birendra N. Agarwala , Aziz M. Ahsan , Arthur Bross , Mark F. Chadurjian , Nicholas G. Koopman , Li-Chung Lee , Karl J. Puttlitz , Sudipta K. Ray , James G. Ryan , Joseph G. Schaefer , Kamalesh K. Srivastava , Paul A. Totta , Erick G. Walton , Adolf E. Wirsing
发明人： Birendra N. Agarwala , Aziz M. Ahsan , Arthur Bross , Mark F. Chadurjian , Nicholas G. Koopman , Li-Chung Lee , Karl J. Puttlitz , Sudipta K. Ray , James G. Ryan , Joseph G. Schaefer , Kamalesh K. Srivastava , Paul A. Totta , Erick G. Walton , Adolf E. Wirsing
IPC分类号： H01L21/60 , H01L23/485 , H05K3/34
CPC分类号： H01L24/13 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/13082 , H01L2224/131 , H01L2224/1357 , H01L2224/13582 , H01L2224/13583 , H01L2224/13647 , H01L2224/13655 , H01L2224/13657 , H01L2224/1366 , H01L2224/13664 , H01L2224/13666 , H01L2224/13669 , H01L2224/1367 , H01L2224/13671 , H01L2224/13672 , H01L2224/13676 , H01L2224/13679 , H01L2224/1368 , H01L2224/13681 , H01L2224/13684 , H01L2224/81801 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01046 , H01L2924/0105 , H01L2924/01051 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/15787 , H05K3/3431 , H05K3/3457
摘要： The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.
摘要翻译：本发明一般涉及新的互连及其制造方法，更具体地说，涉及一种细长的焊料互连及其制造方法。在电子载体上，形成焊盘，在其上沉积焊料块并用金属层封盖，从而形成细长的焊料互连。现在可以通过在已经被金属层覆盖的第一焊料块上形成第二焊料块来形成另外细长的焊料互连。可以通过用金属覆盖层封盖前述焊料块和/或最后的焊料块来形成附加的细长焊料互连。或者，封装层可以是形成在焊料块的侧壁上的侧壁间隔物的形式。

6. 发明授权

US5447264A Recessed via apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon 失效
标题翻译：嵌入式通过用于集成电路芯片的测试，老化和/或编程以及用于在其上放置焊料凸块的装置
公开(公告)号：US5447264A
公开(公告)日：1995-09-05
申请号：US270166
申请日：1994-07-01
申请人： Nicholas G. Koopman , Glenn A. Rinne , Iwona Turlik
发明人： Nicholas G. Koopman , Glenn A. Rinne , Iwona Turlik
IPC分类号： B23K1/00 , H01L21/60 , H01L21/68 , H05K3/34 , B23K3/06 , B23K37/04
CPC分类号： H01L24/11 , B23K1/0016 , H01L21/6835 , H05K3/3473 , H01L2224/11003 , H01L2224/13099 , H01L2224/16 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H05K2201/10734 , H05K2203/0113 , H05K2203/0338 , H05K2203/0726
摘要： A temporary substrate for solder bumps may be used to transfer solder bumps to a microelectronic device. The temporary substrate includes a solder nonwettable surface and a plurality of conductive vias therein. A solder bump is formed on each of the conductive vias and is electrically and mechanically connected thereto. The solder bump extends over the solder nonwettable surface to produce a solder bump cross-sectional area which is greater than the cross-sectional area of the conductive via. A microelectronic device is placed adjacent the temporary substrate with each input/output pad adjacent a respective solder bump. An electrical and mechanical connection is formed between the solder bump and the input/output pad, and the microelectronic device is separated from the temporary substrate with the solder bump remaining connected to the input/output pad. The temporary substrate can also be used for burn-in and testing of microelectronic devices and rework on multichip modules.
摘要翻译：可以使用用于焊料凸块的临时衬底将焊料凸块转移到微电子器件。临时衬底包括焊料不润湿表面和其中的多个导电通孔。在每个导电通孔上形成焊料凸点，并且与其电连接和机械连接。焊料凸块在焊料不可润湿的表面上延伸以产生大于导电通孔的横截面面积的焊料凸块横截面积。微电子器件放置在临时衬底附近，每个输入/输出焊盘与相应的焊料凸块相邻。在焊料凸块和输入/输出焊盘之间形成电气和机械连接，并且微电子器件与临时衬底分离，焊料凸块保持连接到输入/输出焊盘。临时衬底还可用于微电子器件的老化和测试以及多芯片模块上的返工。

7. 发明授权

US5412537A Electrical connector including variably spaced connector contacts 失效
标题翻译：电连接器包括可变间隔的连接器触点
公开(公告)号：US5412537A
公开(公告)日：1995-05-02
申请号：US202348
申请日：1994-02-28
申请人： Paul A. Magill , Nicholas G. Koopman , Glenn A. Rinne
发明人： Paul A. Magill , Nicholas G. Koopman , Glenn A. Rinne
IPC分类号： H01L23/538 , H05K1/02
CPC分类号： H01L23/5383 , H01L2924/0002
摘要： An electrical connector includes a housing and a row of connector contacts coupled to the housing. The row of connector contacts has a predetermined center-to-center spacing between adjacent contacts, with the predetermined center-to-center spacing being relatively large relatively far from an imaginary reference point in the row of connector contacts, and being relatively small relatively near the imaginary reference point in the row of connector contacts. The imaginary reference point is preferably at the center of the row of contacts, and the center-to-center contact spacing preferably progressively increases from the center of the row to the ends of the row. The size of the connector contacts may also progressively increase as well. The electrical connector is preferably adapted for use with a multilayer ceramic substrate which includes a row of capture pads of the same predetermined center-to-center spacing at the edge thereof. The variable center-to-center spacing ensures electrical connection to a conductor filled via in the multilayer ceramic substrate notwithstanding variability and location of the respective via due to shrinkage of the substrate during fabrication thereof.
摘要翻译：电连接器包括壳体和连接到壳体的一排连接器触头。连接器触点列在相邻触点之间具有预定的中心到中心的间隔，其中预定的中心到中心的间隔相对于相对远离连接器触点列中的虚拟参考点相对较大，并且相对较小连接器触点行中的虚拟参考点。虚拟参考点优选地位于触点列的中心，并且中心到中心的接触间隔优选地从行的中心到行的端部逐渐增加。连接器触头的尺寸也可以逐渐增加。电连接器优选适于与多层陶瓷基板一起使用，该多层陶瓷基板在其边缘处包括一排具有相同预定中心间距的捕获垫。尽管在其制造期间由于基板的收缩而导致相应通孔的变化和位置，但是可变的中心到中心间隔确保了与多层陶瓷基板中的经填充的导体的电连接。

8. 发明授权

US5374893A Apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon 失效
标题翻译：用于集成电路芯片的测试，老化和/或编程以及用于在其上放置焊料凸块的装置
公开(公告)号：US5374893A
公开(公告)日：1994-12-20
申请号：US127784
申请日：1993-09-27
申请人： Nicholas G. Koopman , Glenn A. Rinne , Iwona Turlik , Edward K. Yung
发明人： Nicholas G. Koopman , Glenn A. Rinne , Iwona Turlik , Edward K. Yung
IPC分类号： G01R31/26 , G01R31/28 , H01L21/326 , H01L21/66 , H01L23/58 , G01R31/00
CPC分类号： G01R31/2863 , H01L22/32 , H01L2224/0401 , H01L2224/05572 , H01L2224/16 , H01L2924/01014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/15174 , H01L2924/15192 , Y10T29/49144
摘要： An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips. Solder bumps with different characteristics may be formed by varying the current-time product to each individual pad of the temporary substrate during a plating operation.
摘要翻译：可以使用具有对应于芯片上的输入/输出焊盘的位置的衬底焊盘的临时衬底来测试其上具有焊料凸块的集成电路芯片，并且在临时衬底焊盘上具有牺牲导体层。焊料凸点放置在相应的牺牲金属层附近，并被加热以在芯片和临时衬底之间形成电气和机械连接。然后在临时衬底上测试和/或烧入芯片。在测试/老化之后，通过加热将牺牲金属层溶解到焊料凸块中。包括其中具有溶解的牺牲金属层的焊料凸块的集成电路芯片可以容易地从临时衬底移除。也可以在临时衬底上形成焊料凸块并将其转移到未凸起的芯片。可以通过在电镀操作期间通过改变临时衬底的每个单独衬垫的电流时间积来形成具有不同特性的焊料凸块。

9. 发明授权

US4492842A Process of brazing using low temperature braze alloy of gold-indium tin 失效
标题翻译：使用金铟锡低温钎焊合金钎焊工艺
公开(公告)号：US4492842A
公开(公告)日：1985-01-08
申请号：US521286
申请日：1983-08-08
申请人： Nicholas G. Koopman , Vincent C. Marcotte
发明人： Nicholas G. Koopman , Vincent C. Marcotte
IPC分类号： C22C5/02 , B23K35/26 , B23K35/30
CPC分类号： B23K35/3013
摘要： A heat resistant brazing alloy of a major amount of gold, a lesser amount of indium and a minor amount of tin. The alloy is particularly suited for use in bonding electrical components to chip carrying substrates which are to be reworked.
摘要翻译：主要量的金，少量铟和少量锡的耐热钎焊合金。该合金特别适用于将待组装的电气部件与要加工的芯片承载基板结合。

10. 发明授权

US5381946A Method of forming differing volume solder bumps 失效
标题翻译：形成不同体积的焊料凸块的方法
公开(公告)号：US5381946A
公开(公告)日：1995-01-17
申请号：US127785
申请日：1993-09-27
申请人： Nicholas G. Koopman , Glenn A. Rinne , Iwona Turlik , Edward K. Yung
发明人： Nicholas G. Koopman , Glenn A. Rinne , Iwona Turlik , Edward K. Yung
IPC分类号： G01R31/26 , G01R31/28 , H01L21/326 , H01L21/66 , H01L23/58 , H01L21/60
CPC分类号： G01R31/2863 , H01L22/32 , H01L2224/0401 , H01L2224/05572 , H01L2224/16 , H01L2924/01014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/15174 , H01L2924/15192 , Y10T29/49144
摘要： An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips. Solder bumps with different characteristics may be formed by varying the current-time product to each individual pad of the temporary substrate during a plating operation.
摘要翻译：可以使用具有对应于芯片上的输入/输出焊盘的位置的衬底焊盘的临时衬底来测试其上具有焊料凸块的集成电路芯片，并且在临时衬底焊盘上具有牺牲导体层。焊料凸点放置在相应的牺牲金属层附近，并被加热以在芯片和临时衬底之间形成电气和机械连接。然后在临时衬底上测试和/或烧入芯片。在测试/老化之后，通过加热将牺牲金属层溶解到焊料凸块中。包括其中具有溶解的牺牲金属层的焊料凸块的集成电路芯片可以容易地从临时衬底移除。也可以在临时衬底上形成焊料凸块并将其转移到未凸起的芯片。可以通过在电镀操作期间通过改变临时衬底的每个单独衬垫的电流时间积来形成具有不同特性的焊料凸块。

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