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1. 发明授权

US5454161A Through hole interconnect substrate fabrication process 失效
标题翻译：通孔互连基板制造工艺
公开(公告)号：US5454161A
公开(公告)日：1995-10-03
申请号：US54899
申请日：1993-04-29
申请人： Solomon I. Beilin , Michael G. Peters , Michael G. Lee , Wen-chou V. Wang
发明人： Solomon I. Beilin , Michael G. Peters , Michael G. Lee , Wen-chou V. Wang
IPC分类号： H01R11/01 , H01L21/48 , H01L23/498 , H01R43/00 , H05K1/11 , H05K3/40 , H01K3/10
CPC分类号： H01L21/486 , H01L23/49827 , H01L2224/16 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15192 , H01L2924/15311 , H01L2924/15312 , Y10T29/49124 , Y10T29/49144 , Y10T29/49165
摘要： A high density through-hole interconnect with high aspect ratio vias is formed by sequentially forming layers of dielectric material on a previous dielectric layer. After each layer is formed, a plurality of through holes are etched through each layer and filled or metalized with an electrically conductive material having a coefficient of thermal expansion matching that of the dielectric layers and the integrated circuit that it will connect with. Preferably, the process of forming dielectric layers, forming through holes, and metalizing the through holes is repeated until the metalized through holes have an aspect ratio in the range of from 6 to 10. A support structure is constructed to interconnect with and support the metalized vias while the dielectric material is removed. A second dielectric material having the desired mechanical and electrical properties is poured into the support structure to fill the space between the metalized vias and allowed to solidify. The support structure is removed and the through-hole interconnector, comprising the metalized vias and the second dielectric material, is lapped and polished to predetermined manufacturing dimensions and tolerances.
摘要翻译：具有高纵横比通孔的高密度通孔互连通过在先前的介电层上依次形成电介质材料层来形成。在形成每一层之后，通过每个层蚀刻多个通孔，并用与其将连接的电介质层和集成电路的热膨胀系数匹配的导热材料填充或金属化。优选地，重复形成电介质层，形成通孔和使通孔金属化的工艺，直到金属化通孔具有在6至10范围内的纵横比。支撑结构被构造成与金属化的电介质材料被去除时的通孔。将具有期望的机械和电学性能的第二介电材料倒入支撑结构中以填充金属化通孔之间的空间并使其固化。移除支撑结构，并且将包括金属化通孔和第二介电材料的通孔互连器重叠并抛光至预定的制造尺寸和公差。

2. 发明授权

US5323520A Process for fabricating a substrate with thin film capacitor 失效
标题翻译：用薄膜电容器制造衬底的工艺
公开(公告)号：US5323520A
公开(公告)日：1994-06-28
申请号：US054910
申请日：1993-04-29
申请人： Michael G. Peters , William T. Chou , Wen-chou V. Wang , Michael G. Lee , Solomon I. Beilin
发明人： Michael G. Peters , William T. Chou , Wen-chou V. Wang , Michael G. Lee , Solomon I. Beilin
IPC分类号： H01L27/04 , H01G4/232 , H01G4/30 , H01G4/33 , H01L21/822 , H05K1/11 , H05K1/16
CPC分类号： H01G4/232 , H01G4/306 , H05K1/162 , H01L2224/16145 , H01L2224/16225 , H01L2924/1305 , H05K1/112 , H05K2201/0317 , H05K2201/09309 , H05K2203/0315 , Y10T29/435 , Y10T29/49165
摘要： A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed and a bottom contact metalization layer is applied to the surface of the bottom contact layers. A portion of the metalization layer is removed and an insulating layer is formed on the surface of the bottom contact metalization layer. A ground metalization feedthrough and a power metalization feedthrough are formed at the surface of the insulating layer. A sequence of top contact layers are applied to the surface of the insulating layer and a front side ground terminal and front side power terminal are formed. A back side ground terminal and a back side power terminal are formed at the back side of the base substrate.
摘要翻译：通过形成穿过非导电基底基板的厚度的多个通孔并用导电材料填充通孔来形成薄膜旁路电容器，以形成接地通孔和电源通孔。将背面金属化层序列施加到基底基板的背面。底部接触层序列被施加到基底基板的前侧表面。形成底部接触电源端子，并且将底部接触金属化层施加到底部接触层的表面。去除金属化层的一部分，并在底部接触金属化层的表面上形成绝缘层。在绝缘层的表面形成接地金属化馈通和功率金属化馈通。顶层接触层序列被施加到绝缘层的表面，形成前侧接地端子和前端电源端子。背面接地端子和背面电源端子形成在基底基板的背面。

3. 发明授权

US5406446A Thin film capacitor 失效
标题翻译：薄膜电容器
公开(公告)号：US5406446A
公开(公告)日：1995-04-11
申请号：US201628
申请日：1994-02-25
申请人： Michael G. Peters , William T. Chou , Wen-chou V. Wang , Michael G. Lee , Solomon I. Beilin
发明人： Michael G. Peters , William T. Chou , Wen-chou V. Wang , Michael G. Lee , Solomon I. Beilin
IPC分类号： H01L27/04 , H01G4/232 , H01G4/30 , H01G4/33 , H01L21/822 , H05K1/11 , H05K1/16 , H01G1/14
CPC分类号： H01G4/232 , H01G4/306 , H05K1/162 , H01L2224/16145 , H01L2224/16225 , H01L2924/1305 , H05K1/112 , H05K2201/0317 , H05K2201/09309 , H05K2203/0315 , Y10T29/435 , Y10T29/49165
摘要： A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed and a bottom contact metalization layer is applied to the surface of the bottom contact layers. A portion of the metalization layer is removed and an insulating layer is formed on the surface of the bottom contact metalization layer. A ground metalization feedthrough and a power metalization feedthrough are formed at the surface of the insulating layer. A sequence of top contact layers are applied to the surface of the insulating layer and a front side ground terminal and front side power terminal are formed. A back side ground terminal and a back side power terminal are formed at the back side of the base substrate.
摘要翻译：通过形成穿过非导电基底基板的厚度的多个通孔并用导电材料填充通孔来形成薄膜旁路电容器，以形成接地通孔和电源通孔。将背面金属化层序列施加到基底基板的背面。底部接触层序列被施加到基底基板的前侧表面。形成底部接触电源端子，并且将底部接触金属化层施加到底部接触层的表面。去除金属化层的一部分，并在底部接触金属化层的表面上形成绝缘层。在绝缘层的表面形成接地金属化馈通和功率金属化馈通。顶层接触层序列被施加到绝缘层的表面，形成前侧接地端子和前端电源端子。背面接地端子和背面电源端子形成在基底基板的背面。

4. 发明授权

US5544017A Multichip module substrate 失效
标题翻译：多芯片模块基板
公开(公告)号：US5544017A
公开(公告)日：1996-08-06
申请号：US277163
申请日：1994-07-19
申请人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Teruo Murase , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou V. Wang
发明人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Teruo Murase , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou V. Wang
IPC分类号： H01L21/48 , H01L23/473 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14
CPC分类号： H01L21/486 , H01L21/4857 , H01L23/473 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/66 , H01L25/0652 , H05K1/144 , H01L2224/16 , H01L2924/00013 , H01L2924/01019 , H01L2924/01078 , H01L2924/09701 , H01L2924/3011 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204
摘要： A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.
摘要翻译：公开了一种用于三维多芯片模块的多芯片模块基板及其制造方法。衬底包括薄膜结构，用于将信号路由到集成电路芯片上并从集成电路芯片路由到刚性支撑基底上。在支撑基体中形成孔，露出薄膜结构的下侧，从而允许将高密度连接器安装在薄膜结构的两个表面上，大大增强了在芯片模块中的相邻基板之间传递信号的能力。这避免了将信号路由通过刚性支撑底座或薄膜结构的边缘的需要。不需要高连接密度的电源和接地路径通过支持底座的低阻抗路径。优选地，薄膜结构由诸如铜的图案化金属的交替层和诸如聚酰亚胺的低介电有机聚合物制成。

5. 发明授权

US5419038A Method for fabricating thin-film interconnector 失效
标题翻译：制造薄膜互连器的方法
公开(公告)号：US5419038A
公开(公告)日：1995-05-30
申请号：US78461
申请日：1993-06-17
申请人： Wen-chou V. Wang , Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy
发明人： Wen-chou V. Wang , Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy
IPC分类号： H05K1/11 , H05K1/14 , H05K3/00 , H05K3/46 , H05K3/36
CPC分类号： H05K3/4691 , H05K2201/0394 , H05K3/002 , H05K3/0023 , H05K3/0041 , H05K3/467 , Y10T29/49124 , Y10T29/49126 , Y10T29/49165
摘要： A three dimensional thin-film interconnector is fabricated by depositing a dielectric layer onto the surface of a substrate, depositing a layer of conductive material onto the dielectric layer to form a signal plane, depositing a dielectric layer onto the surface of the signal plane, forming a plurality of through holes in the dielectric layer that extend to the signal plane, and filling the through holes with an electrically conductive material to form vias. The sequence of forming a signal plane, depositing a dielectric layer, forming a plurality of through holes, and filling the through holes is repeated until a predetermined number of signal planes and a predetermined arrangement of vias are obtained. The through holes are formed at locations in the dielectric layers corresponding to both predetermined electrical connections and the vias in a preceding dielectric layer. The signal planes are formed at different locations on the substrate. The sequence of signal planes and dielectric layers at the same location on the substrate form a signal plane set which defines a connector. Contact pads are deposited onto the surface of a final dielectric layer and electrically connect with each via. Wires are used to electrically connect the contact pads of one connector to corresponding contact pads of another connector. A portion of the substrate and dielectric layers not comprising a signal plane set is removed, forming electrical connectors flexibly attached by the plurality of wires.
摘要翻译：通过在衬底的表面上沉积介电层来制造三维薄膜互连器，在电介质层上沉积导电材料层以形成信号平面，在信号面的表面上沉积电介质层，形成电介质层中的多个通孔延伸到信号平面，并用导电材料填充通孔以形成通孔。重复形成信号平面，沉积介电层，形成多个通孔和填充通孔的顺序，直到获得预定数量的信号面和通孔的预定布置。通孔形成在电介质层中对应于先前电介质层中的预定电连接和通路两者的位置处。信号面形成在基板上的不同位置。基板上相同位置处的信号平面和电介质层的顺序形成了限定连接器的信号平面组。接触焊盘沉积在最终电介质层的表面上并与每个通孔电连接。电线用于将一个连接器的接触焊盘电连接到另一个连接器的相应接触焊盘。除去不包括信号平面组的衬底和电介质层的一部分，形成由多个电线柔性附接的电连接器。

6. 发明授权

US5474458A Interconnect carriers having high-density vertical connectors and methods for making the same 失效
标题翻译：具有高密度垂直连接器的互连载体及其制造方法
公开(公告)号：US5474458A
公开(公告)日：1995-12-12
申请号：US90701
申请日：1993-07-13
申请人： Habib Vafi , Solomon I. Beilin , Wen-chou V. Wang
发明人： Habib Vafi , Solomon I. Beilin , Wen-chou V. Wang
IPC分类号： H01L23/32 , H01L23/14 , H01L23/498 , H01R4/02 , H01R9/09
CPC分类号： H01L23/49827 , H01L23/49833 , H01L2224/16 , H01L2924/15311 , H01L2924/3011 , H01R4/02
摘要： Interconnect carriers for coupling integrated circuit chips to major substrates and methods for making the same are disclosed. The interconnect carrier comprises a relatively thin resilient supporting layer, a plurality of electrically conductive vias formed through the surfaces of the supporting layer, and an outer frame disposed around the periphery of the supporting layer. The supporting layer preferably comprises an electrically insulating material. The flexibility of the supporting layer enables the layer to more readily conform to the warpages of the IC chip and supporting substrate, while the outer frame provides mechanical support and prevents the supporting layer from folding, twisting, and/or stretching. The thickness of the supporting layer may be substantially reduced over that of prior art interposers to enable methods for constructing smaller diameter vias.
摘要翻译：公开了用于将集成电路芯片耦合到主要基板的互连载体及其制造方法。互连载体包括相对薄的弹性支撑层，通过支撑层的表面形成的多个导电通孔和围绕支撑层的周边设置的外框架。支撑层优选地包括电绝缘材料。支撑层的灵活性使得该层更容易符合IC芯片和支撑基板的翘曲，而外框架提供机械支撑并防止支撑层折叠，扭曲和/或拉伸。支撑层的厚度可以比现有技术的插入件的厚度大大降低，以使得能够构造更小直径的通孔的方法。

7. 发明授权

US5376586A Method of curing thin films of organic dielectric material 失效
标题翻译：固化有机介电材料薄膜的方法
公开(公告)号：US5376586A
公开(公告)日：1994-12-27
申请号：US064224
申请日：1993-05-19
申请人： Solomon I. Beilin , Wen-chou V. Wang , William T. Chou
发明人： Solomon I. Beilin , Wen-chou V. Wang , William T. Chou
IPC分类号： C08G73/10 , H01L21/48 , H01L23/14 , H05K3/46 , H01L21/44
CPC分类号： H05K3/4673 , H01L21/481 , H01L21/4857 , H05K2201/0154 , H05K2203/092 , H05K2203/1105
摘要： A method of curing an organic dielectric layer, such as polyimide, used in a multichip module is disclosed. The method comprises heating the uncured polyimide layer to a temperature above its glass transition temperature, and irradiating the layer with a uniform flux of electrons, as in an e-beam apparatus. The process reduces deterioration at the interface between the dielectric films and the metal layers which when high temperature thermal curing is utilized, and reduces the stress of the resulting film. Multiple dielectric layers can be applied in this manner.
摘要翻译：公开了一种在多芯片模块中使用的固化有机电介质层如聚酰亚胺的方法。该方法包括将未固化的聚酰亚胺层加热至高于其玻璃化转变温度的温度，并且如电子束装置中那样以均匀的电子流照射该层。该方法降低了在使用高温热固化时介电膜和金属层之间的界面处的劣化，并降低了所得膜的应力。可以以这种方式施加多个电介质层。

8. 发明授权

US5455064A Process for fabricating a substrate with thin film capacitor and insulating plug 失效
标题翻译：用薄膜电容器和绝缘插头制造衬底的工艺
公开(公告)号：US5455064A
公开(公告)日：1995-10-03
申请号：US151409
申请日：1993-11-12
申请人： William T. Chou , Michael G. Peters , Wen-chou V. Wang , Richard L. Wheeler
发明人： William T. Chou , Michael G. Peters , Wen-chou V. Wang , Richard L. Wheeler
IPC分类号： H01G4/33 , H01L21/822 , H01L23/12 , H01L23/50 , H01L23/538 , H01L23/64 , H01L27/04 , H05K1/11 , H05K1/16 , H05K3/46 , B05D5/12
CPC分类号： H01L23/50 , H01L23/5383 , H01L23/5384 , H01L23/642 , H05K1/162 , H01L2224/16225 , H01L2924/00013 , H01L2924/09701 , H01L2924/1305 , H01L2924/3011 , H05K1/112 , H05K2201/0317 , H05K2201/09309 , H05K2203/0315
摘要： A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed in the bottom contact layer and is electrically isolated from remaining portions of the bottom contact layers by insulating plugs. A bottom contact metalization layer is applied to the surface of the bottom contact layers and the insulating plugs. A dielectric layer is formed on the surface of the bottom contact metalization layer. A ground metalization via and a power metalization via are formed at the surface of the dielectric layer. A sequence of top contact layers are applied to the surface of the dielectric layer and a front side ground terminal and front side power terminal are formed. A back side ground terminal and a back side power terminal are formed at the back side of the base substrate.
摘要翻译：通过形成穿过非导电基底基板的厚度的多个通孔并用导电材料填充通孔来形成薄膜旁路电容器，以形成接地通孔和电源通孔。将背面金属化层序列施加到基底基板的背面。底部接触层序列被施加到基底基板的前侧表面。底接触电源端子形成在底部接触层中，并且通过绝缘插塞与底部接触层的剩余部分电隔离。底部接触金属化层被施加到底部接触层和绝缘插头的表面。在底部接触金属化层的表面上形成介电层。在电介质层的表面形成有接地金属化通孔和功率金属化通孔。顶层接触层序列被施加到电介质层的表面，形成前侧接地端子和前端电源端子。背面接地端子和背面电源端子形成在基底基板的背面。

9. 发明授权

US5382827A Functional substrates for packaging semiconductor chips 失效
标题翻译：用于封装半导体芯片的功能基板
公开(公告)号：US5382827A
公开(公告)日：1995-01-17
申请号：US927151
申请日：1992-08-07
申请人： Wen-chou V. Wang , William T. Chou
发明人： Wen-chou V. Wang , William T. Chou
IPC分类号： H01L23/538 , H01L23/58 , H01L23/64 , H01L27/02 , H01L23/16 , H01L23/48 , H01L29/41
CPC分类号： H01L23/647 , H01L23/5385 , H01L23/585 , H01L2224/16 , H01L2924/01078 , H01L2924/01079
摘要： A semiconductor chip carrier has a first substrate and at least one second substrate. The first substrate is for carrying at least one semiconductor chip of integrated circuits. The first substrate has predetermined functional elements for connection to the integrated circuits of the at least one semiconductor chip. Such a second substrate is directly coupled to the first substrate. The second substrate is capable of being independently created and has predetermined electrical functional elements for connection to the integrated circuits of the semiconductor chip. The electrical functional elements of each second substrate are of one type and are different than the electrical functional elements of the other second substrates and the first substrate.The second substrate has a top interconnect layer, a bottom interconnect layer, and a plurality of intra-substrate connectors (or through-hole connectors), where the top interconnect layer and the bottom interconnect layer have substantially identical patterns of electrical contacts. The electrical contacts may be deformable bumps, solder bumps, elastomer bumps, or gold bumps.The electrical functional elements are electrically passive circuits, such as capacitors, resistors, or electrical signal conductors. Such a second substrate may include power supply circuits.
摘要翻译：半导体芯片载体具有第一基板和至少一个第二基板。第一衬底用于承载集成电路的至少一个半导体芯片。第一衬底具有用于连接至少一个半导体芯片的集成电路的预定功能元件。这样的第二衬底直接耦合到第一衬底。第二基板能够独立地形成并且具有用于连接到半导体芯片的集成电路的预定的电功能元件。每个第二基板的电功能元件是一种类型的并且不同于其它第二基板和第一基板的电功能元件。第二衬底具有顶部互连层，底部互连层和多个衬底内连接器（或通孔连接器），其中顶部互连层和底部互连层具有基本相同的电触点图案。电触头可以是可变形的凸块，焊料凸块，弹性体凸块或金凸块。电功能元件是诸如电容器，电阻器或电信号导体的无源电路。这样的第二基板可以包括电源电路。

10. 发明授权

US5514906A Apparatus for cooling semiconductor chips in multichip modules 失效
标题翻译：用于冷却多芯片模块中的半导体芯片的装置
公开(公告)号：US5514906A
公开(公告)日：1996-05-07
申请号：US150456
申请日：1993-11-10
申请人： David G. Love , Larry L. Moresco , David A. Horine , Wen-chou V. Wang , Richard L. Wheeler , Patricia R. Boucher , Vivek Mansingh
发明人： David G. Love , Larry L. Moresco , David A. Horine , Wen-chou V. Wang , Richard L. Wheeler , Patricia R. Boucher , Vivek Mansingh
IPC分类号： H01L23/36 , H01L23/44 , H01L23/467 , H01L23/473 , H01L23/34
CPC分类号： H01L23/473 , H01L2224/48091 , H01L2224/48137 , H01L2924/30107 , H01L2924/3025
摘要： A compact, reliable, and efficient cooling system for semiconductor chips is disclosed. In one embodiment, a plurality of semiconductor chips have their active surfaces mounted to a major substrate which provides electrical connections among the chips, and a cooling channel is formed above the major substrate and each chip for conducting a cooling fluid over the back surface of the chips. To increase cooling efficiency, heat sink arrays are formed on the back surfaces of the chips, each array including a plurality of heat conducting elements attached to the back surface. The arrays may be readily and inexpensively constructed with photo-lithography or wire bonding techniques. To control the flow of cooling fluid around the chip edges and to prevent cavitation of the cooling fluid a cavitation and flow control plate disposed at the bottom surface of the cooling channel and formed around the edges of the chips is included. With the increased cooling efficiency, the height of each cooling channel may be substantially reduced to allow close stacking of interconnect substrates for three-dimensional packages and to shorten the vertical communication time between the interconnect substrates.
摘要翻译：公开了一种用于半导体芯片的紧凑，可靠和高效的冷却系统。在一个实施例中，多个半导体芯片的主动表面安装在提供芯片之间的电连接的主要基板上，并且在主基板上方形成冷却通道，并且每个芯片用于在冷却流体的背面筹码为了提高冷却效率，在芯片的背面形成有散热片阵列，每个阵列包括连接到背面的多个导热元件。阵列可以用光刻或引线键合技术容易且廉价地构造。为了控制芯片边缘周围的冷却流体的流动，并且为了防止冷却流体的气蚀，包括设置在冷却通道的底表面处并形成在芯片边缘周围的空化和流量控制板。随着冷却效率的提高，每个冷却通道的高度可以被显着地减小，以允许用于三维封装的互连衬底的紧密堆叠并且缩短互连衬底之间的垂直通信时间。

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