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1. 发明授权

US06870782B2 Row redundancy memory repair scheme with shift to eliminate timing penalty 有权
标题翻译：行冗余存储器修复方案转移以消除定时损失
公开(公告)号：US06870782B2
公开(公告)日：2005-03-22
申请号：US10414516
申请日：2003-04-15
申请人： Sifang Wu , Ghasi R. Agrawal , Kevin R. LeClair
发明人： Sifang Wu , Ghasi R. Agrawal , Kevin R. LeClair
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/848
摘要： A memory having built-in self repair with row shifting is provided. The rows in the memory are divided into smaller row groups and a bad row group is repaired with a redundant row group. Each row group receives a row select signal, which is fed into a shift circuit for the row group and a shift circuit for an adjacent row group. A shift circuit is provided for the redundant row group and the shift circuit for the redundant row group receives the row select signal for only the adjacent row group. If a bad row group is detected, then starting with the row group furthest from the redundant row group, the shift circuit for each row group before the bad row group is deactivated. The row group select signal and word line signal for the bad row group are disabled. The shift circuit for the bad row group and the shift circuit for each row group after the bad row group are activated. Therefore, the bad row group is disabled and the redundant row group fills the void.
摘要翻译：提供了具有行移位的内置自修复记忆体。存储器中的行被划分成较小的行组，并且使用冗余行组修复坏行组。每行组接收行选择信号，其被馈送到用于行组的移位电路和用于相邻行组的移位电路。为冗余行组提供移位电路，并且用于冗余行组的移位电路仅接收相邻行组的行选择信号。如果检测到错误的行组，则从离冗余行组最远的行组开始，则不良行组之前的每个行组的移位电路都将被禁用。不良行组的行组选择信号和字线信号被禁用。不良行组的移位电路和坏行组之后的每个行组的移位电路都被激活。因此，不良行组被禁用，冗余行组填充空白。

2. 发明授权

US07260758B1 Method and system for performing built-in self-test routines using an accumulator to store fault information 有权
标题翻译：使用累加器执行内置自检程序来存储故障信息的方法和系统
公开(公告)号：US07260758B1
公开(公告)日：2007-08-21
申请号：US09949399
申请日：2001-09-07
申请人： Ghasi R. Agrawal , Mukesh K. Puri , William Schwarz
发明人： Ghasi R. Agrawal , Mukesh K. Puri , William Schwarz
IPC分类号： G01R31/28
CPC分类号： G11C29/56 , G11C29/56008
摘要： A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the memory array to detect the presence of any faulty memory address locations that may arise under the prevailing stress condition. A full testing cycle involves iterative repetition of the functions performed by the stress applicator and BIST circuit, with variations in the stress factors across the testing iterations. An accumulator cumulatively stores the fault information generated by the BIST circuit during each testing iteration. Following completion of the testing cycle, a repair operation is performed by a built-in self-repair (BISR) circuit to remap the faulty memory address locations indicated by the accumulator to redundant memory address locations.
摘要翻译：测试系统包括内置自检（BIST）电路和用于分析存储器阵列的应力施加器。应力施加器向存储器阵列施加选择性的一组应力因子，例如温度和电压条件。 BIST电路在存储器阵列上执行测试程序，以检测在当前应力条件下可能出现的任何故障存储器地址位置的存在。完整的测试周期包括由应力施加器和BIST电路执行的功能的迭代重复，并且跨越测试迭代的应力因子的变化。累加器在每个测试迭代期间累积地存储由BIST电路产生的故障信息。在完成测试周期之后，通过内置自修复（BISR）电路执行修复操作，将由累加器指示的故障存储器地址位置重新映射到冗余存储器地址位置。

3. 发明授权

US06871297B2 Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories 失效
标题翻译：开机状态机实现与计数器控制扫描产品与硬BISR记忆
公开(公告)号：US06871297B2
公开(公告)日：2005-03-22
申请号：US10120670
申请日：2002-04-11
申请人： Mukesh K. Puri , Ghasi R. Agrawal
发明人： Mukesh K. Puri , Ghasi R. Agrawal
IPC分类号： G06F11/00 , G11C29/00 , G11C29/16 , G11C29/44 , H04B1/74
CPC分类号： G11C29/44 , G11C29/16 , G11C29/4401 , G11C29/789
摘要： An apparatus comprising a controller circuit and a BISR assembly circuit. The controller circuit may be configured to present one or more control signals. The control signals may be configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation. The BISR assembly circuit generally comprises one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution during the BIST and BISR operations. The memory blocks may be remapped in response to the count values during one or more of the BISR operations.
摘要翻译：一种包括控制器电路和BISR组装电路的装置。控制器电路可以被配置为呈现一个或多个控制信号。控制信号可以被配置为控制一个或多个内置自检（BIST）和内置自修复（BISR）操作模式。 BISR组装电路通常包括一个或多个存储器块，每个存储块包括被配置为在BIST和BISR操作期间响应于修复解决方案产生时钟周期计数值的计数器。响应于在一个或多个BISR操作期间的计数值可以重新映射存储器块。

4. 发明授权

US06404700B1 Low power high density asynchronous memory architecture 有权
标题翻译：低功耗高密度异步存储器架构
公开(公告)号：US06404700B1
公开(公告)日：2002-06-11
申请号：US09880491
申请日：2001-06-13
申请人： Ghasi R. Agrawal
发明人： Ghasi R. Agrawal
IPC分类号： G11C800
CPC分类号： G11C8/16
摘要： An architecture for a low power, high density (smaller area) asynchronous memory comprises memory cells including a forward inverter and a feedback inverter disposed in a back-to-back arrangement (i.e., back-to-back inverters), two write access transistors, a read inverter, and a read access transistor. The architecture employs a double ended write into the memory cells wherein Write Bit Lines coupled to write access transistors are precharged to Vdd−Vtn, or, alternately Vdd, when the signal Write Enable (WE) is low (i.e., “0”).
摘要翻译：用于低功率，高密度（较小面积）异步存储器的架构包括存储单元，其包括以背对背布置（即背对背反向器）设置的正向反相器和反馈反相器，两个写入存取晶体管读取反相器和读取存取晶体管。该结构采用双端写入存储器单元，其中耦合到写存取晶体管的写位线被预充电到Vdd-Vtn，或者当信号写使能（WE）为低（即“0”）时交替地为Vdd。

5. 发明授权

US07640152B2 Accurate pin-based memory power model using arc-based characterization 失效
标题翻译：使用基于电弧的表征的精确的基于引脚的存储器功率模型
公开(公告)号：US07640152B2
公开(公告)日：2009-12-29
申请号：US12150846
申请日：2008-05-01
申请人： Jia-Lih J. Chen , Naveen Gupta , Ghasi R. Agrawal
发明人： Jia-Lih J. Chen , Naveen Gupta , Ghasi R. Agrawal
IPC分类号： G06F7/60 , G06F7/50 , G06G7/54
CPC分类号： G06F17/5036 , G06F2217/78
摘要： A pin-based memory power modeling method using arc-based characterization includes steps as follows. All power arcs of a memory model are identified and characterized. A power arc is selected from the identified and characterized power arcs. Output bus switching power is computed by removing overlapping power using the selected power arc, and a temporary value for various input ramp times and output loads is derived. Output pin power for the selected power arc is calculated using the temporary value and a ratio of a number of output bits switching over an entire bus width. Switching power for the selected power arc is calculated by a power estimation tool based on port activity and an input intrinsic power value.
摘要翻译：使用基于电弧的表征的基于引脚的存储器功率建模方法包括以下步骤。识别和表征存储器模型的所有功率弧。从识别的和表征的功率弧中选择电弧。通过使用所选择的功率电弧去除重叠的功率来计算输出总线开关功率，并导出各种输入斜坡时间和输出负载的临时值。使用临时值和输出位数在整个总线宽度上切换的比例来计算所选功率电弧的输出引脚功率。通过基于端口活动和输入固有功率值的功率估计工具来计算所选功率弧的开关功率。

6. 发明授权

US07493541B1 Method and system for performing built-in-self-test routines using an accumulator to store fault information 失效
标题翻译：使用累加器来执行内置自检程序来存储故障信息的方法和系统
公开(公告)号：US07493541B1
公开(公告)日：2009-02-17
申请号：US11824264
申请日：2007-06-29
申请人： Ghasi R. Agrawal , Mukesh K. Puri , William Schwarz
发明人： Ghasi R. Agrawal , Mukesh K. Puri , William Schwarz
IPC分类号： G01R31/28
CPC分类号： G11C29/56 , G11C29/56008
摘要： A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the memory array to detect the presence of any faulty memory address locations that may arise under the prevailing stress condition. A full testing cycle involves iterative repetition of the functions performed by the stress applicator and BIST circuit, with variations in the stress factors across the testing iterations. An accumulator cumulatively stores the fault information generated by the BIST circuit during each testing iteration. Following completion of the testing cycle, a repair operation is performed by a built-in self-repair (BISR) circuit to remap the faulty memory address locations indicated by the accumulator to redundant memory address locations.
摘要翻译：测试系统包括内置的自检（BIST）电路和用于分析存储器阵列的应力施加器。应力施加器向存储器阵列施加选择性的一组应力因子，例如温度和电压条件。 BIST电路在存储器阵列上执行测试程序，以检测在当前应力条件下可能出现的任何故障存储器地址位置的存在。完整的测试周期包括由应力施加器和BIST电路执行的功能的迭代重复，并且跨越测试迭代的应力因子的变化。累加器在每个测试迭代期间累积地存储由BIST电路产生的故障信息。在完成测试周期之后，通过内置自修复（BISR）电路执行修复操作，将由累加器指示的故障存储器地址位置重新映射到冗余存储器地址位置。

7. 发明授权

US06643204B1 Self-time scheme to reduce cycle time for memories 有权
标题翻译：自我时间计划，以减少记忆的循环时间
公开(公告)号：US06643204B1
公开(公告)日：2003-11-04
申请号：US10209483
申请日：2002-07-31
申请人： Ghasi R. Agrawal
发明人： Ghasi R. Agrawal
IPC分类号： G11C1604
CPC分类号： G11C7/227 , G11C7/22 , G11C8/18
摘要： A self-time circuit and method are presented for reducing the write cycle time in a semiconductor memory. A “dummy” memory cell having the same timing requirements as the functional cells, and associated write logic are added to the standard circuitry of the memory device. The dummy write cell receives the same control signals used to write data to the functional cells of the memory, and is configured to issue a completion signal when a write access is concluded, causing the write cycle to be terminated. The circuit and method permits write cycle time to be reduced to the lowest practical value, independently of the read cycle time. This potentially increases the overall operating speed of the memory device. The circuit and method disclosed herein are adaptable to the most common types of memory devices, such as SRAM, DRAM and CAM.
摘要翻译：提出了一种用于减少半导体存储器中的写周期时间的自身时间电路和方法。具有与功能单元相同的定时要求的相应写入逻辑的“虚拟”存储器单元被添加到存储器件的标准电路中。虚拟写单元接收用于将数据写入存储器的功能单元的相同控制信号，并且被配置为当写访问结束时发出完成信号，导致写周期终止。电路和方法允许写周期时间降低到最低实际值，而与读周期时间无关。这可能增加存储器件的总体操作速度。本文公开的电路和方法适用于诸如SRAM，DRAM和CAM之类的最常见类型的存储器件。

8. 发明授权

US06640321B1 Built-in self-repair of semiconductor memory with redundant row testing using background pattern 有权
标题翻译：内置自修复半导体存储器，冗余行测试采用背景图案
公开(公告)号：US06640321B1
公开(公告)日：2003-10-28
申请号：US09549621
申请日：2000-04-14
申请人： Johnnie A. Huang , Ghasi R. Agrawal
发明人： Johnnie A. Huang , Ghasi R. Agrawal
IPC分类号： G11C2900
CPC分类号： G11C29/24 , G11C29/44 , G11C2029/0405
摘要： A method is presented for self-test and self-repair of a semiconductor memory device. Prior to the self-repair stage, both redundant and regular memory portions are comprehensively tested, preferably using a checkerboard bit pattern. Faulty rows identified in each memory portion during testing are recorded. Known-bad rows in regular memory are then replaced by known-good redundant rows in the self-repair stage, and the resulting repaired memory is retested for verification. Compared to existing methods, the new method is believed to provide improved test coverage, making it both more effective in identifying non-repairable memory devices and less prone to fail repairable ones.
摘要翻译：提出了一种用于半导体存储器件的自检和自修复的方法。在自修复阶段之前，冗余和常规存储器部分被全面测试，优选地使用棋盘位图案。在测试期间记录每个存储器部分中识别的错误行。常规内存中的已知坏行随后在自修复阶段被已知良好的冗余行替换，并重新测试生成的修复内存以进行验证。与现有的方法相比，这种新方法被认为可以提供更好的测试覆盖范围，使其更有效地识别不可修复的存储器件，并且不太可能发生故障可修复的器件。

9. 发明授权

US07076699B1 Method for testing semiconductor devices having built-in self repair (BISR) memory 有权
标题翻译：用于测试具有内置自修复（BISR）存储器的半导体器件的方法
公开(公告)号：US07076699B1
公开(公告)日：2006-07-11
申请号：US09956302
申请日：2001-09-19
申请人： Mukesh K. Puri , Ghasi R. Agrawal , William Schwarz
发明人： Mukesh K. Puri , Ghasi R. Agrawal , William Schwarz
IPC分类号： G11C29/00
CPC分类号： G11C17/165 , G11C29/027 , G11C29/12015 , G11C29/44 , G11C29/4401 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C2029/4402
摘要： A method for testing semiconductor devices advantageously increases manufacturing yields. The method includes generating memory repair data for a wafer die by writing at least one predetermined digital bit pattern into a memory on the wafer die, reading the at least one predetermined digital bit pattern back out of the memory, comparing the at least one predetermined digital bit pattern read out from the memory against the at least one predetermined digital bit pattern written into the memory, and storing results of the comparison as the memory repair data. The writing and reading are performed a plurality of times, each time with a different voltage and clock frequency combination being applied to the wafer die. The memory repair data is programmed into the wafer die, and the wafer die is assembled into a packaged semiconductor device. The packaged semiconductor device is tested by causing the memory repair data programmed within the packaged semiconductor device to be transferred into the memory a plurality of times, each time with a different voltage and clock frequency combination being applied to the packaged semiconductor device.
摘要翻译：用于测试半导体器件的方法有利地提高了制造成品率。该方法包括通过将至少一个预定的数字位模式写入晶片管芯上的存储器来产生晶片管芯的存储器修复数据，将至少一个预定的数字位模式读出存储器，将至少一个预定的数字位模式从写入存储器的至少一个预定的数字位模式从存储器读出的位模式，并将比较的结果存储为存储器修复数据。执行写入和读取多次，每次以不同的电压和时钟频率组合施加到晶片管芯。将存储器修复数据编程到晶片管芯中，将晶片管芯组装成封装的半导体器件。通过使封装的半导体器件中编程的存储器修复数据被多次传送到封装的半导体器件中，每次都将不同的电压和时钟频率组合应用于封装的半导体器件。

10. 发明授权

US06366508B1 Integrated circuit memory having column redundancy with no timing penalty 有权
标题翻译：集成电路存储器具有列冗余，无定时损失
公开(公告)号：US06366508B1
公开(公告)日：2002-04-02
申请号：US09729020
申请日：2000-12-04
申请人： Ghasi R. Agrawal , Jerry K. Tanaka
发明人： Ghasi R. Agrawal , Jerry K. Tanaka
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/846
摘要： A memory array includes a zone of memory elements and a column multiplexer. The zone of memory elements is arranged in rows and columns, including a set of non-redundant columns and a redundant column. The column multiplexer has a section coupled to the set of non-redundant columns and to the redundant column. The column multiplexer has a selectable non-redundant path through the section for each of the non-redundant columns and a selectable redundant path for the redundant column. The redundant path is interchangeable with any one of the non-redundant paths.
摘要翻译：存储器阵列包括存储器元件区和列复用器。存储器元件区域以行和列排列，包括一组非冗余列和冗余列。列多路复用器具有耦合到该非冗余列和冗余列的部分。列多路复用器具有用于每个非冗余列的该部分的可选择的非冗余路径和冗余列的可选冗余路径。冗余路径可与任何一个非冗余路径互换。

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