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1. 发明申请

US20120262661A1 LIQUID CRYSTAL COMPOSITION AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME 有权
标题翻译：液晶组合物和液晶显示器，包括它们
公开(公告)号：US20120262661A1
公开(公告)日：2012-10-18
申请号：US13237783
申请日：2011-09-20
申请人： Si-Heun KIM , Seong-Nam LEE , Duck-Jong SUH , Ji-Eun JANG , Jae-Weon HUR
发明人： Si-Heun KIM , Seong-Nam LEE , Duck-Jong SUH , Ji-Eun JANG , Jae-Weon HUR
IPC分类号： C09K19/02 , C09K19/20 , C09K19/34 , C09K19/30 , C09K19/12
CPC分类号： C09K19/44 , C09K2019/0466 , C09K2019/123 , C09K2019/3016 , C09K2019/3025 , C09K2019/3422
摘要： A liquid crystal composition according to an exemplary embodiment of the present invention includes a liquid crystal compound represented by a below chemical formula (I) at about 10 wt % to about 15 wt %; and at least one liquid crystal compound at about 3 wt % to about 8 wt % among liquid crystal compounds represented by chemical formula (II) to chemical formula (IV). Here, X and Y may be equal to each other or different from each other, and each is an alkyl group or an alkenyl group having a carbon number of 1 to 4.
摘要翻译：根据本发明的示例性实施方案的液晶组合物包含以下述化学式（I）表示的液晶化合物：约10重量％至约15重量％和由化学式（II）表示为化学式（IV）的液晶化合物中的至少一种液晶化合物为约3重量％至约8重量％。这里，X和Y可以彼此相同或不同，并且各自为碳数为1〜4的烷基或烯基。

2. 发明申请

US20090045883A1 SELF REFRESH OSCILLATOR AND OSCILLATION SIGNAL GENERATION METHOD OF THE SAME 有权
标题翻译：自激振荡器及其振荡信号生成方法
公开(公告)号：US20090045883A1
公开(公告)日：2009-02-19
申请号：US12255074
申请日：2008-10-21
申请人： Ji-Eun JANG
发明人： Ji-Eun JANG
IPC分类号： H03K3/03 , H03L1/00
CPC分类号： G11C11/406 , G11C2211/4065
摘要： A self refresh period signal generator includes: a voltage detection unit for detecting a voltage level of a power supply voltage in order to generate a plurality of period control signals according to the detected voltage level; and an oscillation unit for generating a ring oscillation signal having a constant period determined by a resistance of a period control resistor when a self refresh signal is activated, wherein the resistance of the period control resistor is controlled according to logic levels of the plurality of period control signals.
摘要翻译：自刷新周期信号发生器包括：电压检测单元，用于检测电源电压的电压电平，以便根据检测的电压电平产生多个周期控制信号; 以及振荡单元，用于当自刷新信号被激活时产生具有由周期控制电阻器的电阻确定的恒定周期的环形振荡信号，其中周期控制电阻器的电阻根据多个周期的逻辑电平进行控制控制信号。

3. 发明申请

US20130107646A1 SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF 有权
标题翻译：半导体器件及其测试方法
公开(公告)号：US20130107646A1
公开(公告)日：2013-05-02
申请号：US13333715
申请日：2011-12-21
申请人： Bo-Yeun KIM , Ji-Eun JANG
发明人： Bo-Yeun KIM , Ji-Eun JANG
IPC分类号： G11C7/00
CPC分类号： G11C29/785 , G11C29/802 , G11C2029/4402
摘要： A semiconductor device comprises a plurality of cell blocks activated in response to a plurality of selection signals, respectively, a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and activate at least two of the pre-selection signals by decoding addresses in a multi-test mode, a selection signal controller configured to selectively activate the plurality of selection signals in response to the plurality pre-selection signals and control active periods of the activated selection signals so as not to overlap, and a decision circuit configured to decide whether or not the cell blocks activated in response to the activated selection signals are repaired in response to stored repair information and the plurality of selection signals.
摘要翻译：半导体器件分别包括响应于多个选择信号被激活的多个单元块，预选择信号发生器被配置为分别产生与单元块相对应的多个预选信号，并激活至少两个通过在多测试模式中解码地址来选择预选信号，选择信号控制器被配置为响应于多个预选信号选择性地激活多个选择信号，并且控制所激活的选择信号的有效期，以便不以及判定电路，其被配置为响应于所存储的修复信息和所述多个选择信号来确定响应于所激活的选择信号而被激活的单元块是否被修复。

4. 发明申请

US20090116313A1 DATA OUTPUT CONTROL CIRCUIT 失效
标题翻译：数据输出控制电路
公开(公告)号：US20090116313A1
公开(公告)日：2009-05-07
申请号：US11967595
申请日：2007-12-31
申请人： Ji-Eun JANG
发明人： Ji-Eun JANG
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066
摘要： A data output control circuit includes a data output control circuit configured to compensate a delay amount of a system clock on a clock path when a delay locked loop (DLL) circuit is enabled in such a state that the semiconductor memory device exits a reset state in response to an active signal, and to determine an output timing of data corresponding to a read command by counting the system clock and a DLL clock outputted from the DLL circuit 0 when the DLL circuit 0 is disabled, without compensating the delay amount.
摘要翻译：数据输出控制电路包括：数据输出控制电路，被配置为当在半导体存储器件退出复位状态的状态下使能延迟锁定环（DLL）电路时，补偿时钟路径上的系统时钟的延迟量响应于活动信号，并且在DLL电路0被禁用时，通过对系统时钟和从DLL电路0输出的DLL时钟进行计数来确定与读命令相对应的数据的输出定时，而不补偿延迟量。

5. 发明申请

US20090172479A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME 有权
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US20090172479A1
公开(公告)日：2009-07-02
申请号：US12181700
申请日：2008-07-29
申请人： Ji-Eun JANG , Seok-Cheol YOON
发明人： Ji-Eun JANG , Seok-Cheol YOON
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/48 , G11C7/1006 , G11C7/1078 , G11C29/1201 , G11C29/14
摘要： A semiconductor memory device includes an alignment unit configured to align data received from the outside, a plurality of data input/output lines corresponding to the aligned data, respectively and a realignment unit configured to change correspondence between the data and the data input/output lines in response to one or more change signals in a test mode. A method for testing the semiconductor memory device includes inputting data in series using a testing apparatus, aligning the serial data in parallel, and realigning the parallel data in response to one or more change signals.
摘要翻译：一种半导体存储器件，包括对准单元，被配置为对准从外部接收的数据，分别对应于对准的数据的多个数据输入/输出线以及重新对准单元，其被配置为改变数据和数据输入/输出线之间的对应关系响应于测试模式中的一个或多个改变信号。用于测试半导体存储器件的方法包括使用测试装置串联输入数据，并行地对齐串行数据，以及响应于一个或多个改变信号重新对准并行数据。

6. 发明申请

US20090115449A1 ON DIE TERMINATION DEVICE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：打印终端装置和包括其的半导体存储装置
公开(公告)号：US20090115449A1
公开(公告)日：2009-05-07
申请号：US12181628
申请日：2008-07-29
申请人： Ki-Ho KIM , Ji-Eun JANG
发明人： Ki-Ho KIM , Ji-Eun JANG
IPC分类号： H03K19/003
CPC分类号： G11C5/063 , G11C7/1051 , G11C7/1057 , G11C2207/2254
摘要： On die termination (ODT) device that can reduce the number of lines for transferring calibration codes to reduce the size of a chip including the ODT device. The ODT device includes a calibration circuit configured to generate calibration codes for determining a termination resistance, a counting circuit configured to generate counting codes increasing with time. A transferring circuit of the device is configured sequentially to transfer the calibration codes in response to the counting codes. A receiving circuit is configured sequentially to receive the calibration codes from the transferring circuit in response to the counting codes. A termination resistance circuit of the device is configured to perform impedance matching using a resistance determined according to the calibration codes.
摘要翻译：在终端（ODT）设备上，可以减少用于传送校准码的行数，以减少包括ODT设备在内的芯片的尺寸。 ODT装置包括：校准电路，被配置为产生用于确定终止电阻的校准码;计数电路，被配置为产生随时间增加的计数码。依次配置设备的传送电路以响应于计数代码传送校准代码。接收电路被顺序配置以响应于计数代码从传送电路接收校准码。该器件的终端电阻电路被配置为使用根据校准码确定的电阻来执行阻抗匹配。

7. 发明申请

US20090327573A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20090327573A1
公开(公告)日：2009-12-31
申请号：US12265951
申请日：2008-11-06
申请人： Ji-Eun JANG
发明人： Ji-Eun JANG
IPC分类号： G06F12/06
CPC分类号： G11C7/1006 , G11C5/066 , G11C7/1012 , G11C7/1048
摘要： A semiconductor memory device, including a memory banks and associated local data buses, and a bus connection circuit connected to the local data buses associated with two or more of the memory banks to perform a selective data transfer between a global data bus and those local data buses.
摘要翻译：包括存储器组和相关联的本地数据总线的半导体存储器件以及连接到与两个或更多个存储体相关联的本地数据总线的总线连接电路，以在全局数据总线和那些本地数据之间执行选择性数据传输巴士

8. 发明申请

US20090322387A1 OUTPUT ENABLE SIGNAL GENERATION CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：用于半导体存储器件的输出使能信号生成电路
公开(公告)号：US20090322387A1
公开(公告)日：2009-12-31
申请号：US12326572
申请日：2008-12-02
申请人： Ji-Eun JANG , Seok-Cheol Yoon
发明人： Ji-Eun JANG , Seok-Cheol Yoon
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , G11C7/1051 , G11C7/1066
摘要： A circuit for generating an output enable signal includes a reset signal generator for synchronizing a reset signal with an external clock signal to generate an output enable (OE) reset signal, synchronizers for synchronizing the OE reset signal with an internal clock signal to generate a source reset signal, and an output enable signal output unit, reset by the source reset signal, for counting pulses of the external clock signal and the internal clock signal to output an output enable signal corresponding to a read command and CAS latency.
摘要翻译：用于产生输出使能信号的电路包括用于使复位信号与外部时钟信号同步以产生输出使能（OE）复位信号的复位信号发生器，用于使OE复位信号与内部时钟信号同步以产生源复位信号和由源复位信号复位的输出使能信号输出单元，用于计数外部时钟信号和内部时钟信号的脉冲，以输出对应于读取命令和CAS延迟的输出使能信号。

9. 发明申请

US20090002003A1 PROBE-TESTING DEVICE AND METHOD OF SEMICONDUCTOR DEVICE 失效
标题翻译：探测器件和半导体器件的方法
公开(公告)号：US20090002003A1
公开(公告)日：2009-01-01
申请号：US11967729
申请日：2007-12-31
申请人： Ki-Ho KIM , Ji-Eun JANG
发明人： Ki-Ho KIM , Ji-Eun JANG
IPC分类号： G01R31/26 , G01R35/00
CPC分类号： G01R35/005 , G01R1/06766 , G01R1/06772 , G01R31/3191
摘要： A probe-testing device includes probe tips configured to apply inputs to pads of a semiconductor chip, wherein one of the probe tips is connected to a calibration pad for impedance adjustment and a calibration resistor is connected thereto.
摘要翻译：探针测试装置包括被配置为向半导体芯片的焊盘施加输入的探针尖端，其中探针尖端中的一个连接到用于阻抗调节的校准焊盘，并且校准电阻器被连接到其上。

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