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1. 发明授权

US08785241B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08785241B2
公开(公告)日：2014-07-22
申请号：US13174960
申请日：2011-07-01
申请人： Shinya Sasagawa , Hitoshi Nakayama , Masashi Tsubuku , Daigo Shimada
发明人： Shinya Sasagawa , Hitoshi Nakayama , Masashi Tsubuku , Daigo Shimada
IPC分类号： H01L21/44 , H01L21/336
CPC分类号： H01L29/66969 , H01L22/14 , H01L27/088 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/45 , H01L29/4908 , H01L29/7869
摘要： When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.
摘要翻译：当制造具有底栅底接触结构的晶体管时，例如，构成源极和漏极的导电层具有三层结构，并且执行两步蚀刻。在第一蚀刻工艺中，采用其中至少第二膜和第三膜的蚀刻速率高的蚀刻方法，并且进行第一蚀刻处理直到至少第一膜暴露。在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面提供并与第一膜接触的”层的蚀刻速率的蚀刻方法低于采用第一蚀刻工艺。当在第二蚀刻工艺之后去除抗蚀剂掩模时，第二膜的侧壁被稍微蚀刻。

2. 发明授权

US08637354B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08637354B2
公开(公告)日：2014-01-28
申请号：US13159804
申请日：2011-06-14
申请人： Shinya Sasagawa , Hitoshi Nakayama , Masashi Tsubuku , Daigo Shimada
发明人： Shinya Sasagawa , Hitoshi Nakayama , Masashi Tsubuku , Daigo Shimada
IPC分类号： H01L21/00 , H01L29/04
CPC分类号： H01L29/7869 , H01L29/45 , H01L29/66969
摘要： When a transistor including a conductive layer having a three-layer structure is manufactured, three-stage etching is performed. In the first etching process, an etching method in which the etching rates for the second film and the third film are high is employed, and the first etching process is performed until the first film is at least exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. In the third etching process, an etching method in which the etching rates for the first to the third films are higher than those in the second etching process is preferably employed.
摘要翻译：当制造包括具有三层结构的导电层的晶体管时，进行三级蚀刻。在第一蚀刻工艺中，采用其中第二膜和第三膜的蚀刻速率高的蚀刻方法，并且执行第一蚀刻处理直到第一膜至少暴露。在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于采用第一蚀刻工艺。在第三蚀刻工艺中，优选使用其中第一至第三膜的蚀刻速率高于第二蚀刻工艺中的蚀刻速率的蚀刻方法。

3. 发明授权

US08597992B2 Transistor and manufacturing method of the same 有权
标题翻译：晶体管及其制造方法相同
公开(公告)号：US08597992B2
公开(公告)日：2013-12-03
申请号：US13026520
申请日：2011-02-14
申请人： Shinya Sasagawa , Masashi Tsubuku , Hitoshi Nakayama , Daigo Shimada
发明人： Shinya Sasagawa , Masashi Tsubuku , Hitoshi Nakayama , Daigo Shimada
IPC分类号： H01L21/00
CPC分类号： H01L21/76838 , H01L21/32136 , H01L21/32139 , H01L29/66969 , H01L29/7869
摘要： A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.
摘要翻译：晶体管通过以下方法制造：包括：形成第一布线层; 形成第一绝缘膜以覆盖所述第一布线层; 在所述第一绝缘膜上形成半导体层; 在半导体层上形成导电膜; 并且对所述导电膜进行蚀刻的至少两个步骤以形成彼此分离的第二布线层，其中所述两个蚀刻步骤至少包括在导电膜的蚀刻速率为高于半导体层的蚀刻速率，以及在导电膜和半导体层的蚀刻速率高于第一蚀刻工艺的蚀刻速率的条件下进行的第二蚀刻工艺。

4. 发明授权

US09799773B2 Transistor and semiconductor device 有权
公开(公告)号：US09799773B2
公开(公告)日：2017-10-24
申请号：US13358556
申请日：2012-01-26
申请人： Hiromichi Godo , Satoshi Kobayashi , Masashi Tsubuku
发明人： Hiromichi Godo , Satoshi Kobayashi , Masashi Tsubuku
IPC分类号： H01L29/78 , H01L29/786 , H01L29/423
CPC分类号： H01L29/7869 , H01L29/42384
摘要： A transistor which withstands a high voltage and controls large electric power can be provided. A transistor is provided which includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode, and a source electrode and a drain electrode which are in contact with the oxide semiconductor layer and whose end portions overlap with the gate electrode. The gate insulating layer includes a first region overlapping with the end portion of the drain electrode and a second region adjacent to the first region. The first region has smaller capacitance than the second region.

5. 发明授权

US09437743B2 Thin film element, semiconductor device, and method for manufacturing the same 有权
标题翻译：薄膜元件，半导体器件及其制造方法
公开(公告)号：US09437743B2
公开(公告)日：2016-09-06
申请号：US13237191
申请日：2011-09-20
申请人： Takafumi Mizoguchi , Kojiro Shiraishi , Masashi Tsubuku
发明人： Takafumi Mizoguchi , Kojiro Shiraishi , Masashi Tsubuku
IPC分类号： H01L29/786 , H01L21/764 , H01L27/12
CPC分类号： H01L29/78606 , H01L21/764 , H01L27/1225 , H01L27/1288 , H01L29/24 , H01L29/7869 , H01L29/78696
摘要： An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.
摘要翻译：本发明的目的是提供一种制造半导体器件的方法，而不会将特定层暴露于湿气等。制造薄膜元件，使得第一膜，第二膜和第三膜按此顺序堆叠; 在第三膜上形成抗蚀剂掩模; 通过使用抗蚀剂掩模蚀刻第三膜来形成掩模层; 去除抗蚀剂掩模; 通过使用掩模层对第二膜和第一膜进行干蚀刻来形成第二层和第一层; 形成第四膜至少覆盖第二层和第一层; 并且通过在第四膜上进行回蚀而形成侧壁层以至少覆盖第一层的整个侧表面。

6. 发明授权

US09082858B2 Transistor including an oxide semiconductor and display device using the same 有权
标题翻译：包括氧化物半导体的晶体管和使用其的显示装置
公开(公告)号：US09082858B2
公开(公告)日：2015-07-14
申请号：US13026511
申请日：2011-02-14
申请人： Masashi Tsubuku , Kosei Noda
发明人： Masashi Tsubuku , Kosei Noda
IPC分类号： H01L29/12 , H01L27/15 , H01L29/786 , H01L27/12
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/156
摘要： The band tail state and defects in the band gap are reduced as much as possible, whereby optical absorption of energy which is in the vicinity of the band gap or less than or equal to the band gap is reduced. In that case, not by merely optimizing conditions of manufacturing an oxide semiconductor film, but by making an oxide semiconductor to be a substantially intrinsic semiconductor or extremely close to an intrinsic semiconductor, defects on which irradiation light acts are reduced and the effect of light irradiation is reduced essentially. That is, even in the case where light with a wavelength of 350 nm is delivered at 1×1013 photons/cm2·sec, a channel region of a transistor is formed using an oxide semiconductor, in which the absolute value of the amount of the variation in the threshold voltage is less than or equal to 0.65 V.
摘要翻译：频带尾部状态和带隙中的缺陷尽可能地减小，由此减小了在带隙附近或小于或等于带隙的能量的光吸收。在这种情况下，不是仅通过优化氧化物半导体膜的制造条件，而是通过使氧化物半导体成为本质上的本征半导体，或者非常接近本征半导体，减少照射光的作用的缺陷和光照射基本上减少了。也就是说，即使在以1×1013个光子/ cm 2·sec传递波长为350nm的光的情况下，也可以使用氧化物半导体形成晶体管的沟道区域，其中，阈值电压的变化小于或等于0.65 V.

7. 发明授权

US08625085B2 Defect evaluation method for semiconductor 有权
标题翻译：半导体缺陷评估方法
公开(公告)号：US08625085B2
公开(公告)日：2014-01-07
申请号：US13407943
申请日：2012-02-29
申请人： Ryosuke Watanabe , Masashi Tsubuku , Takayuki Inoue
发明人： Ryosuke Watanabe , Masashi Tsubuku , Takayuki Inoue
IPC分类号： G01N21/00
CPC分类号： H01L22/14 , H01L22/12
摘要： Even in the case of a sample exhibiting low photoresponse, such as a wide bandgap semiconductor, a measurement method which enables highly accurate CPM measurement is provided. When CPM measurement is performed, photoexcited carriers which are generated by light irradiation of a sample exhibiting low photoresponse such as a wide bandgap semiconductor are instantly removed by application of positive bias voltage to a third electrode which is provided in the sample in addition to two electrodes used for measurement. When the photoexcited carriers are removed, even in the case of the sample exhibiting low photoresponse, the controllability of a photocurrent value is improved and CPM measurement can be performed accurately.
摘要翻译：即使在具有低光响应的样品（例如宽带隙半导体）的情况下，也提供了能够进行高度精确的CPM测量的测量方法。当进行CPM测量时，通过向除了两个电极之外的样品中提供的第三电极施加正偏置电压，立即除去通过光照射出具有低光响应的样品（例如宽带隙半导体）产生的光激发载流子用于测量。当除去光激发载体时，即使在样品表现出较低的光响应的情况下，光电流值的可控性得到改善，也可以精确地进行CPM测量。

8. 发明授权

US08421067B2 Oxide semiconductor device 有权
标题翻译：氧化物半导体器件
公开(公告)号：US08421067B2
公开(公告)日：2013-04-16
申请号：US12846572
申请日：2010-07-29
申请人： Shunpei Yamazaki , Masashi Tsubuku , Kengo Akimoto , Miyuki Hosoba , Junichiro Sakata
发明人： Shunpei Yamazaki , Masashi Tsubuku , Kengo Akimoto , Miyuki Hosoba , Junichiro Sakata
IPC分类号： H01L29/12
CPC分类号： H01L29/78696 , H01L27/1225 , H01L29/7869
摘要： A semiconductor device having a structure which enables sufficient reduction in parasitic capacitance is provided. In addition, the operation speed of thin film transistors in a driver circuit is improved. In a bottom-gate thin film transistor in which an oxide insulating layer is in contact with a channel formation region in an oxide semiconductor layer, a source electrode layer and a drain electrode layer are formed in such a manner that they do not overlap with a gate electrode layer. Thus, the distance between the gate electrode layer and the source electrode layer and between the gate electrode layer and the drain electrode layer are increased; accordingly, parasitic capacitance can be reduced.
摘要翻译：提供具有能够充分降低寄生电容的结构的半导体器件。此外，提高了驱动电路中薄膜晶体管的操作速度。在其中氧化物绝缘层与氧化物半导体层中的沟道形成区域接触的底栅薄膜晶体管中，以与它们不重叠的方式形成源电极层和漏电极层栅电极层。因此，栅极电极层与源电极层之间以及栅极电极层和漏极电极层之间的距离增加; 因此，可以减小寄生电容。

9. 发明授权

US08400187B2 Logic circuit and semiconductor device 有权
标题翻译：逻辑电路和半导体器件
公开(公告)号：US08400187B2
公开(公告)日：2013-03-19
申请号：US12901057
申请日：2010-10-08
申请人： Shunpei Yamazaki , Jun Koyama , Masashi Tsubuku , Kosei Noda
发明人： Shunpei Yamazaki , Jun Koyama , Masashi Tsubuku , Kosei Noda
IPC分类号： H01L25/00 , H03K19/094 , H03B1/00
CPC分类号： H01L29/7869 , H01L22/34 , H01L27/0207 , H01L27/1225 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.
摘要翻译：逻辑电路包括具有使用氧化物半导体形成的沟道形成区域的薄膜晶体管，以及通过关闭薄膜晶体管而使端子中的一个成为浮置状态的电容器。氧化物半导体的氢浓度为5×1019（原子/ cm3）以下，因此在不产生电场的状态下基本上用作绝缘体。因此，可以减小薄膜晶体管的截止电流，从而通过薄膜晶体管抑制存储在电容器中的电荷的泄漏。因此，可以防止逻辑电路的故障。此外，可以通过减小薄膜晶体管的截止电流来降低在逻辑电路中流动的过量的电流，导致逻辑电路的低功耗。

10. 发明授权

US08383470B2 Thin film transistor (TFT) having a protective layer and manufacturing method thereof 有权
标题翻译：具有保护层的薄膜晶体管（TFT）及其制造方法
公开(公告)号：US08383470B2
公开(公告)日：2013-02-26
申请号：US12634084
申请日：2009-12-09
申请人： Kengo Akimoto , Masashi Tsubuku
发明人： Kengo Akimoto , Masashi Tsubuku
IPC分类号： H01L21/84 , H01L27/14 , H01L29/04 , H01L29/15 , H01L31/036
CPC分类号： H01L33/0041 , H01L29/66969 , H01L29/78606 , H01L29/78618 , H01L29/7869 , H01L2924/0002 , H01L2924/00
摘要： One of factors that increase the contact resistance at the interface between a first semiconductor layer where a channel is formed and source and drain electrode layers is a film with high electric resistance formed by dust or impurity contamination of a surface of a metal material serving as the source and drain electrode layers. As a solution, a first protective layer and a second protective layer including a second semiconductor having a conductivity that is less than or equal to that of the first semiconductor layer is stacked successively over source and drain electrode layers without exposed to air, the stack of films is used for the source and drain electrode layers.
摘要翻译：增加在形成沟道的第一半导体层与源电极层与漏极电极层之间的界面处的接触电阻的因素之一是具有高电阻的膜，其由作为金属材料的金属材料的表面的灰尘或杂质污染形成源极和漏极电极层。作为解决方案，包括导电率小于或等于第一半导体层的导电率的第二半导体的第一保护层和第二保护层在不暴露于空气的情况下在源极和漏极电极层上依次层叠，膜用于源电极层和漏电极层。

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