专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4972078A Pulse generating circuit for detecting aperture size of camera shutter 失效
标题翻译：用于检测相机快门光圈尺寸的脉冲发生电路
公开(公告)号：US4972078A
公开(公告)日：1990-11-20
申请号：US339266
申请日：1989-04-17
申请人： Shinichi Hasebe , Masayuki Sasaki
发明人： Shinichi Hasebe , Masayuki Sasaki
IPC分类号： H03K3/02 , G01D5/347 , G03B7/097 , H03K3/42
CPC分类号： G03B7/097
摘要： In at least one of a plurality of shutter vanes forming a shutter there are provided a plurality of openings adapted to detect the movement of the shutter vanes. A photointerrupter is turned on and off by the openings when the shutter vanes move. An output voltage of the photointerrupter is compared with a reference voltage by a comparator. A series combination of a switch, which is turned on and off by the output voltage of the comparator, and a resistor is connected between the output of the photointerrupter and ground. The output signal of the comparator is delayed. The delayed version and the output signal of the comparator are exclusive ORed to produce a train of pulses corresponding to the openings as the shutter vanes move. A drive and control section is responsive to the count of the pulses to control the operation of the shutter.

2. 发明授权

US07457383B2 Receiving LSI device and receiver using the same 失效
标题翻译：接收使用LSI的LSI设备和接收器
公开(公告)号：US07457383B2
公开(公告)日：2008-11-25
申请号：US11159338
申请日：2005-06-23
申请人： Shinichi Hasebe , Masahiro Abe
发明人： Shinichi Hasebe , Masahiro Abe
IPC分类号： H04B7/10 , H04L1/02
CPC分类号： H04L1/0065 , H04B7/0871 , H04L1/0045 , H04L1/203 , H04L1/208 , Y02D70/444
摘要： A receiving large scale integrated circuit (LSI) device, including a demodulator which includes two signal processing circuits to demodulate two diversity signals to form a demodulated signal, a decoder which decodes the demodulated signal in accordance with an error correcting code to form a decoded signal, a receiving quality judgment circuit which codes the decoded signal to form a re-coded signal as a reference signal, compares the demodulated signal with the reference signal to obtain an error rate of the two diversity signals and supplies a judgment signal depending on the error rate, and a control circuit which selects one of the two signal processing circuits or both two signal processing circuits in response to the judgment signal of the receiving quality judgment circuit and stops supplying electric power or a clock signal to the one of the two processing circuits not selected by the control circuit.
摘要翻译：一种接收大规模集成电路（LSI）装置，包括解调器，其包括用于解调两个分集信号以形成解调信号的两个信号处理电路，解码器，其根据纠错码对解调信号进行解码以形成解码信号对解码信号进行编码以形成作为参考信号的重新编码信号的接收质量判断电路，将解调信号与参考信号进行比较，以获得两个分集信号的错误率，并根据误差提供判断信号速率和控制电路，其响应于接收质量判断电路的判断信号选择两个信号处理电路中的一个或两个信号处理电路，并停止向两个处理电路之一提供电力或时钟信号未被控制电路选择。

3. 发明授权

US07126371B2 Multi-function IC card 有权
标题翻译：多功能IC卡
公开(公告)号：US07126371B2
公开(公告)日：2006-10-24
申请号：US10327513
申请日：2002-12-20
申请人： Hiroo Nakano , Shinichi Hasebe
发明人： Hiroo Nakano , Shinichi Hasebe
IPC分类号： G06F7/38 , G06F11/00 , G06F1/26 , G06F1/28 , G06F1/30
CPC分类号： G06K19/07703 , G06F1/30 , G06F21/71 , G06K7/0008 , G06K19/0701 , G06K19/0719 , G06K19/0723
摘要： When a reset signal /RESET is “L”, a flip-flop circuit holds “1”; on the other hand, a flip-flop circuit holds “0”. When the reset signal /RESET becomes “H”, the flip-flop circuits captures data in synchronous with a clock signal. When a power supply voltage returns to the initial value after an instantaneous blackout occurs, the data of the flip-flop circuits have the same value. An output signal of an exclusive-OR gate circuit becomes “L”, the output is held in a flip-flop circuit. As a result, an instantaneous blackout detection signal becomes “H”.
摘要翻译：复位信号/ RESET为“L”时，触发电路保持“1”。另一方面，触发电路保持“0”。当复位信号/ RESET变为“H”时，触发器电路与时钟信号同步捕获数据。当电源电压在瞬时停电发生后恢复到初始值时，触发器电路的数据具有相同的值。异或门电路的输出信号为“L”，输出保持在触发电路中。结果，瞬时停电检测信号成为“H”。

4. 发明申请

US20050286658A1 Receiving LSI device and receiver using the same 失效
标题翻译：接收使用LSI的LSI设备和接收器
公开(公告)号：US20050286658A1
公开(公告)日：2005-12-29
申请号：US11159338
申请日：2005-06-23
申请人： Shinichi Hasebe , Masahiro Abe
发明人： Shinichi Hasebe , Masahiro Abe
IPC分类号： H03M13/03 , H04B7/08 , H04L1/00 , H04L1/02 , H04L1/20 , H04L27/06
CPC分类号： H04L1/0065 , H04B7/0871 , H04L1/0045 , H04L1/203 , H04L1/208 , Y02D70/444
摘要： Diversity receiver 100 provided with receiving LSI device 10, antennas 11 and 12, RF circuits 25 and 26 and main CPU 27 is disclosed. Receiving LSI device 10 receives diversity signals through antennas 11 and 12 and RF circuits 25 and 26. One of ADCs 30 and 31 and a part of CDM 32 provided in demodulator 14 are only energized to save electric power consumption when a receiving quality of the diversity signals is acceptable, or both ADCs 30 and 31 and CDM 32 are otherwise fully energized. Bit-interleave circuit 15, Viterbi decoder 17 and receiving-quality-judgment circuit 19 connected in parallel with Viterbi decoder 17 are provided to detect an error rate for the receiving quality judgment. Further, byte-interleave circuit 20, Reed-Solomon decoder 22 and receiving-quality-judgment circuit 24 connected in parallel with Reed-Solomon decoder 22 are also provided to detect another error rate for the receiving quality judgment. Main CPU 27 is connected to receiving LSI device 10 to supply demodulator 14 with a control signal based on the error rates detected by receiving quality judgment circuits 19 and 24.
摘要翻译：公开了设置有接收LSI装置10，天线11和12，RF电路25和26以及主CPU27的分集接收器100。接收LSI装置10通过天线11,12和RF电路25,26接收分集信号。 ADC 30和31中的一个以及在解调器14中提供的CDM32的一部分仅在分集信号的接收质量可接受时，或者ADC 30和31以及CDM 32另外完全通电时才被激励以节省电力消耗。提供与维特比解码器17并联连接的位交织电路15，维特比解码器17和接收质量判断电路19，以检测接收质量判断的错误率。此外，还提供与Reed-Solomon解码器22并联连接的字节交错电路20，里德 - 所罗门解码器22和接收质量判断电路24，以检测接收质量判断的另一错误率。主CPU27连接到接收LSI装置10，以向解调器14提供基于由接收质量判断电路19和24检测到的错误率的控制信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式