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1. 发明授权

US07741948B2 Laminated variable resistor 有权
标题翻译：层压可变电阻器
公开(公告)号：US07741948B2
公开(公告)日：2010-06-22
申请号：US11540606
申请日：2006-10-02
申请人： Shih-Kwan Liu , Hui-Ming Feng
发明人： Shih-Kwan Liu , Hui-Ming Feng
IPC分类号： H01C7/00
CPC分类号： H01C7/112 , H01C7/18
摘要： A laminated variable resistor comprises a main body, internal electrodes extending along two side edges of the main body into the main body, terminal electrodes disposed on the two ends of the main body. The mole percentage of the oxide in overlapping active regions between opposite internal electrodes is reduced and the reduced portion is replaced by a metal selected from gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), or the alloy of any two of such metals.
摘要翻译：层叠可变电阻器包括：主体，沿着主体的两个侧边缘延伸到主体的内部电极，设置在主体的两端的端子电极。在相对的内部电极之间的重叠活性区域中的氧化物的摩尔百分比减小，并且还原部分被选自金（Au），银（Ag），钯（Pd），铂（Pt），铑（Rh ）或任何两种这样的金属的合金。

2. 发明申请

US20080079532A1 Laminated variable resistor 有权
标题翻译：层压可变电阻器
公开(公告)号：US20080079532A1
公开(公告)日：2008-04-03
申请号：US11540606
申请日：2006-10-02
申请人： Shih-Kwan Liu , Hui-Ming Feng
发明人： Shih-Kwan Liu , Hui-Ming Feng
IPC分类号： H01C7/00
CPC分类号： H01C7/112 , H01C7/18
摘要： A laminated variable resistor comprises a main body, internal electrodes extending along two side edges of the main body into the main body, terminal electrodes disposed on the two ends of the main body. The mole percentage of the oxide in overlapping active regions between opposite internal electrodes is reduced and the reduced portion is replaced by a metal selected from gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), or the alloy of any two of such metals.
摘要翻译：层叠可变电阻器包括：主体，沿着主体的两个侧边缘延伸到主体的内部电极，设置在主体的两端的端子电极。在相对的内部电极之间的重叠活性区域中的氧化物的摩尔百分比减小，并且还原部分被选自金（Au），银（Ag），钯（Pd），铂（Pt），铑（Rh ）或任何两种这样的金属的合金。

3. 发明申请

US20090233112A1 MULTILAYER ZINC OXIDE VARISTOR 审中-公开
标题翻译：多层氧化锌系列
公开(公告)号：US20090233112A1
公开(公告)日：2009-09-17
申请号：US12047335
申请日：2008-03-13
申请人： Shih-Kwan Liu , Hui-Ming Feng
发明人： Shih-Kwan Liu , Hui-Ming Feng
IPC分类号： B32B15/04
CPC分类号： H01C7/112
摘要： Enclosed is a multilayer zinc oxide (ZnO) varistor having a body portion, internal electrodes extending from both sides to the interior of the body portion respectively, and terminal electrodes disposed at both sides of the body portion. The multilayer zinc oxide is characterized in that: the components of said body portion include at least 90 mole % ZnO, 0.1 to 5.0 mole % antimony oxide functional additives, 0.01 to 1.0 mole % praseodymium oxide functional additives, and 0.01 to 10.0 wt. % glass; the sum amount of these metal oxides is less than 99.95 mole %.
摘要翻译：封闭的是多层氧化锌（ZnO）变阻器，其具有主体部分，分别从主体部分的两侧延伸到内部电极的内部电极以及设置在主体部分两侧的端子电极。多层氧化锌的特征在于：所述主体部分的组分包括至少90摩尔％的ZnO，0.1至5.0摩尔％的氧化锑功能添加剂，0.01至1.0摩尔％的氧化镨功能添加剂和0.01至10.0重量％％玻璃; 这些金属氧化物的总量小于99.95摩尔％。

4. 发明申请

US20060234022A1 Ceramic glaze coating structure of a chip element and method of forming the same 审中-公开
标题翻译：一种芯片元件的陶瓷釉料涂层结构及其形成方法
公开(公告)号：US20060234022A1
公开(公告)日：2006-10-19
申请号：US11403777
申请日：2006-04-13
申请人： Shih-Kwan Liu , Chun-Pin Huang , Yu-Chin Shu
发明人： Shih-Kwan Liu , Chun-Pin Huang , Yu-Chin Shu
IPC分类号： H01G4/228 , H01G4/06 , B32B18/00
CPC分类号： H01G4/30 , H01G2/22 , H01G4/2325 , H01G4/255 , Y10T428/24926
摘要： A ceramic glaze-coating structure of a chip element and a method of forming the same are provided. In the ceramic glaze-coating structure, a high-density, smooth, and high-impedance ceramic glaze is coated on the body of an element. As for the terminal electrode part, the unique firing characteristics between the material of the terminal electrode (e.g., conductive compositions) and the ceramic glaze are utilized, such that the ceramic glaze layer between the surface of the terminal electrode or the terminal electrode and the ceramic body is absorbed and then removed by sintering; thus, the ceramic glaze coating structure of a chip element with only the element body being coated is formed.
摘要翻译：提供了一种芯片元件的陶瓷釉面结构及其形成方法。在陶瓷釉面结构中，高密度，平滑和高阻抗的陶瓷釉料涂覆在元件的主体上。对于端子电极部分，利用端子电极（例如，导电组合物）的材料和陶瓷釉料之间的独特的烧制特性，使得在端子电极或端子电极的表面之间的陶瓷釉层和陶瓷体被吸收，然后通过烧结除去; 因此，形成仅具有被涂覆元件体的芯片元件的陶瓷釉涂层结构。

5. 发明授权

US06965167B2 Laminated chip electronic device and method of manufacturing the same 有权
标题翻译：层压芯片电子器件及其制造方法
公开(公告)号：US06965167B2
公开(公告)日：2005-11-15
申请号：US10463200
申请日：2003-06-17
申请人： Shih-Kwan Liu
发明人： Shih-Kwan Liu
IPC分类号： H01G4/224 , H01G4/232 , H01G4/30 , H01L23/48
CPC分类号： H01G4/30 , H01G4/224 , H01G4/232
摘要： The present invention discloses a laminated chip electronic device and a method of manufacturing the same. In the laminated chip electronic device and the method of manufacturing the same according to the present invention, a body is made of a non-linear resistance coefficient material and has a plurality of conductive layers formed therein; an insulating layer is formed on the top, bottom, front and back surfaces of the body; and two electrodes are formed at the two ends of the body and electrically connected to the terminals of the conductive layers, respectively. Furthermore, in the present invention, two soldered interface layers are formed on the two electrodes, respectively.
摘要翻译：本发明公开了一种层叠芯片电子器件及其制造方法。在根据本发明的层叠芯片电子器件及其制造方法中，主体由非线性电阻系数材料制成并且在其中形成有多个导电层; 绝缘层形成在主体的顶部，底部，前后表面上; 并且在主体的两端分别形成两个电极，并分别与导电层的端子电连接。此外，在本发明中，在两个电极上分别形成两个焊接界面层。

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