专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08669597B2 Memory device interconnects and method of manufacturing 有权
标题翻译：存储器件互连和制造方法
公开(公告)号：US08669597B2
公开(公告)日：2014-03-11
申请号：US12116200
申请日：2008-05-06
申请人： Shenqing Fang , Connie Wang , Wen Yu , Fei Wang
发明人： Shenqing Fang , Connie Wang , Wen Yu , Fei Wang
IPC分类号： H01L29/66 , H01L21/4763
CPC分类号： H01L23/528 , H01L21/76807 , H01L21/76813 , H01L27/115 , H01L27/11519 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.
摘要翻译：在一个实施例中，集成电路存储器件包括具有多个位线的衬底。第一和第二层间电介质层依次设置在基板上。多个源极线和交错位线触点中的每一个延伸穿过第一层间电介质层。多个源极线路通孔和多个交错位线通孔中的每一条通过第二级间介电层延伸到多条源极线路和多条交错位线触点中的每一个。通过第一组制造工艺一起形成延伸穿过第一层间电介质层的源极线和交错位线触点。延伸穿过第二层间电介质层的源极线通孔和交错位线触点也通过第二组制造工艺一起形成。

2. 发明授权

US07867899B2 Wordline resistance reduction method and structure in an integrated circuit memory device 有权
标题翻译：集成电路存储器件中的字线电阻降低方法和结构
公开(公告)号：US07867899B2
公开(公告)日：2011-01-11
申请号：US12111886
申请日：2008-04-29
申请人： Shenqing Fang , Jihwan Choi , Connie Wang , Eunha Kim
发明人： Shenqing Fang , Jihwan Choi , Connie Wang , Eunha Kim
IPC分类号： H01L21/44 , H01L21/02
CPC分类号： H01L27/11573 , G11C5/063 , H01L21/823468 , H01L27/1052 , H01L27/11526 , H01L27/11531 , H01L29/665 , H01L29/66507
摘要： Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.
摘要翻译：公开了用于降低集成电路存储器件的字线中的电阻的方法和结构。在一个实施例中，该方法包括在相应数量的字线上形成多列多晶硅，形成与字线相关联的核心晶体管结和外围晶体管结，对外围晶体管结执行盐化处理，并对多晶硅从字线低电阻。

3. 发明授权

US09240418B2 Wordline resistance reduction method and structure in an integrated circuit memory device 有权
标题翻译：集成电路存储器件中的字线电阻降低方法和结构
公开(公告)号：US09240418B2
公开(公告)日：2016-01-19
申请号：US12961379
申请日：2010-12-06
申请人： Shenqing Fang , Jihwan Choi , Connie Wang , Eunha Kim
发明人： Shenqing Fang , Jihwan Choi , Connie Wang , Eunha Kim
IPC分类号： H01L21/00 , H01L27/115 , G11C5/06 , H01L27/105 , H01L29/66 , H01L21/8234
CPC分类号： H01L27/11573 , G11C5/063 , H01L21/823468 , H01L27/1052 , H01L27/11526 , H01L27/11531 , H01L29/665 , H01L29/66507
摘要： Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.
摘要翻译：公开了用于降低集成电路存储器件的字线中的电阻的方法和结构。在一个实施例中，该方法包括在相应数量的字线上形成多列多晶硅，形成与字线相关联的核心晶体管结和外围晶体管结，对外围晶体管结执行盐化处理，并对多晶硅从字线低电阻。

4. 发明申请

US20100078815A1 Ruthenium interconnect with high aspect ratio and method of fabrication thereof 有权
标题翻译：具有高纵横比的钌互连及其制造方法
公开(公告)号：US20100078815A1
公开(公告)日：2010-04-01
申请号：US12286149
申请日：2008-09-29
申请人： Zheng Wang , Connie Wang , Erik Wilson , Wen Yu , Robert Chiu
发明人： Zheng Wang , Connie Wang , Erik Wilson , Wen Yu , Robert Chiu
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L23/485 , H01L21/76877 , H01L23/53252 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11517 , H01L2924/0002 , H01L2924/00
摘要： An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or greater is achievable.
摘要翻译：导电互连通过介电层中的开口设置，电连接两个导电层。在一个实施例中，互连由完全填充介电层中的开口的钌形成。在另一个实施方案中，在提供钌之前，在开口中提供钛的粘附层。在使用这种方法时，可实现20:1或更大的纵横比（互连长度与其宽度之比）。

5. 发明授权

US09299643B2 Ruthenium interconnect with high aspect ratio and method of fabrication thereof 有权
标题翻译：具有高纵横比的钌互连及其制造方法
公开(公告)号：US09299643B2
公开(公告)日：2016-03-29
申请号：US12286149
申请日：2008-09-29
申请人： Zheng Wang , Connie Wang , Erik Wilson , Wen Yu , Robert Chiu
发明人： Zheng Wang , Connie Wang , Erik Wilson , Wen Yu , Robert Chiu
IPC分类号： H01L29/40 , H01L23/485 , H01L21/768 , H01L23/532 , H01L27/105 , H01L27/115
CPC分类号： H01L23/485 , H01L21/76877 , H01L23/53252 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11517 , H01L2924/0002 , H01L2924/00
摘要： An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or greater is achievable.
摘要翻译：导电互连通过介电层中的开口设置，电连接两个导电层。在一个实施例中，互连由完全填充介电层中的开口的钌形成。在另一个实施方案中，在提供钌之前，在开口中提供钛的粘附层。在使用这种方法时，可实现20:1或更大的纵横比（互连长度与其宽度之比）。

6. 发明授权

US10561217B1 Breakage resistant light bulb headband 有权
公开(公告)号：US10561217B1
公开(公告)日：2020-02-18
申请号：US16205650
申请日：2018-11-30
申请人： Connie Wang
发明人： Connie Wang
IPC分类号： A45D8/36 , F21V23/02 , F21V17/16 , F21V23/00 , F21W121/06 , F21V23/04
摘要： A breakage resistant light bulb headband having increased flexibility includes a single piece injection-molded main body with integral bulb holding structures, a clip-on battery case, and wiring that connects light sources and a power source in the battery case by extending along an outside surface of the headband so as to eliminate the need for an internal passage, and a relatively thick multiple piece construction.

7. 发明申请

US20050085073A1 Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition 失效
标题翻译：使用化学气相沉积（CVD）铜沉积的粘附前体层的方法
公开(公告)号：US20050085073A1
公开(公告)日：2005-04-21
申请号：US10687186
申请日：2003-10-16
申请人： Sergey Lopatin , Paul Besser , Alline Myers , Jeremias Romero , Minh Tran , Lu You , Connie Wang
发明人： Sergey Lopatin , Paul Besser , Alline Myers , Jeremias Romero , Minh Tran , Lu You , Connie Wang
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76846 , H01L21/76877
摘要： An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.
摘要翻译：示例性实施例涉及在集成电路制造工艺中使用粘附前体的方法。该方法包括在介电材料上提供材料的气体并在粘附前体层上提供铜层。粘附前体层由气体形成，电介质材料包括孔。

8. 发明授权

US11039674B2 Breakage resistant light bulb headband 有权
公开(公告)号：US11039674B2
公开(公告)日：2021-06-22
申请号：US16748984
申请日：2020-01-22
申请人： Connie Wang
发明人： Connie Wang
IPC分类号： A45D8/36 , F21V23/02 , F21V17/16 , F21V23/00 , F21W121/06 , F21V23/04
摘要： A breakage resistant light bulb headband having increased flexibility includes a single piece injection-molded main body with integral bulb holding structures, a clip-on battery case, and wiring that connects light sources and a power source in the battery case by extending along an outside surface of the headband so as to eliminate the need for an internal passage, and a relatively thick multiple piece construction.

9. 外观设计

USD698958S1 Luminous stick 有权
公开(公告)号：USD698958S1
公开(公告)日：2014-02-04
申请号：US29439866
申请日：2012-12-17
申请人： Connie Wang , Wei Hung Yu
设计人： Connie Wang , Wei Hung Yu

10. 发明授权

US07838429B2 Method to manufacture a thin film resistor 有权
标题翻译：制造薄膜电阻的方法
公开(公告)号：US07838429B2
公开(公告)日：2010-11-23
申请号：US11779465
申请日：2007-07-18
申请人： Tony Phan , Kyle M. Flessner , Martin B. Mollat , Connie Wang , Arthur Pan , Eric William Beach , Michelle R. Keramidas , Karen Elizabeth Burks
发明人： Tony Phan , Kyle M. Flessner , Martin B. Mollat , Connie Wang , Arthur Pan , Eric William Beach , Michelle R. Keramidas , Karen Elizabeth Burks
IPC分类号： H01L21/302
CPC分类号： H01L28/20 , H01L21/8221 , H01L27/0688
摘要： A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters.
摘要翻译：一种用于制造半导体器件的方法，该方法包括通过包括在半导体衬底上沉积电阻材料层的工艺来形成薄膜电阻器。该方法还包括在电阻材料层上沉积绝缘层，以及在绝缘层上进行第一干蚀刻工艺以形成绝缘体。该方法还包括在电阻材料层上执行第二干蚀刻工艺以形成电阻体。电阻体和绝缘体具有基本相同的周长。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式