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    • 1. 发明授权
    • Memory device interconnects and method of manufacturing
    • 存储器件互连和制造方法
    • US08669597B2
    • 2014-03-11
    • US12116200
    • 2008-05-06
    • Shenqing FangConnie WangWen YuFei Wang
    • Shenqing FangConnie WangWen YuFei Wang
    • H01L29/66H01L21/4763
    • H01L23/528H01L21/76807H01L21/76813H01L27/115H01L27/11519H01L27/11524H01L2924/0002H01L2924/00
    • An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.
    • 在一个实施例中,集成电路存储器件包括具有多个位线的衬底。 第一和第二层间电介质层依次设置在基板上。 多个源极线和交错位线触点中的每一个延伸穿过第一层间电介质层。 多个源极线路通孔和多个交错位线通孔中的每一条通过第二级间介电层延伸到多条源极线路和多条交错位线触点中的每一个。 通过第一组制造工艺一起形成延伸穿过第一层间电介质层的源极线和交错位线触点。 延伸穿过第二层间电介质层的源极线通孔和交错位线触点也通过第二组制造工艺一起形成。