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1. 发明授权

US07836220B2 Network direct memory access 有权
标题翻译：网络直接内存访问
公开(公告)号：US07836220B2
公开(公告)日：2010-11-16
申请号：US11505736
申请日：2006-08-17
申请人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
发明人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
IPC分类号： G06F13/28 , G06F15/16 , G06F15/167
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.
摘要翻译：在一个实施例中，系统包括耦合到网络的至少第一节点和第二节点。第二节点包括本地存储器和耦合到本地存储器的直接存储器访问（DMA）控制器。第一节点被配置为将至少第一分组发送到第二节点以访问本地存储器中的数据和至少一个未被编码以访问本地存储器的其他分组。第二节点被配置为从协议栈的数据链路层捕获分组，并且其中DMA控制器被配置为执行与本地存储器的一次或多次传输，以响应于第一分组访问由第一分组指定的数据从数据链路层接收。第二个节点被配置为将另一个分组处理到协议栈的顶部。

2. 发明授权

US08495257B2 Network direct memory access 有权
标题翻译：网络直接内存访问
公开(公告)号：US08495257B2
公开(公告)日：2013-07-23
申请号：US12908741
申请日：2010-10-20
申请人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
发明人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
IPC分类号： G06F13/28 , G06F15/167
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.
摘要翻译：在一个实施例中，系统包括耦合到网络的至少第一节点和第二节点。第二节点包括本地存储器和耦合到本地存储器的直接存储器访问（DMA）控制器。第一节点被配置为将至少第一分组发送到第二节点以访问本地存储器中的数据和至少一个未被编码以访问本地存储器的其他分组。第二节点被配置为从协议栈的数据链路层捕获分组，并且其中DMA控制器被配置为响应于接收到的第一分组而与本地存储器执行多一次传输以访问由第一分组指定的数据从数据链路层。第二个节点被配置为将另一个分组处理到协议栈的顶部。

3. 发明申请

US20110035459A1 Network Direct Memory Access 有权
标题翻译：网络直接内存访问
公开(公告)号：US20110035459A1
公开(公告)日：2011-02-10
申请号：US12908741
申请日：2010-10-20
申请人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
发明人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
IPC分类号： G06F15/167
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.
摘要翻译：在一个实施例中，系统包括耦合到网络的至少第一节点和第二节点。第二节点包括本地存储器和耦合到本地存储器的直接存储器访问（DMA）控制器。第一节点被配置为将至少第一分组发送到第二节点以访问本地存储器中的数据和至少一个未被编码以访问本地存储器的其他分组。第二节点被配置为从协议栈的数据链路层捕获分组，并且其中DMA控制器被配置为执行与本地存储器的一次或多次传输，以响应于第一分组访问由第一分组指定的数据从数据链路层接收。第二个节点被配置为将另一个分组处理到协议栈的顶部。

4. 发明申请

US20080043732A1 Network direct memory access 有权
标题翻译：网络直接内存访问
公开(公告)号：US20080043732A1
公开(公告)日：2008-02-21
申请号：US11505736
申请日：2006-08-17
申请人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
发明人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
IPC分类号： H04L12/56
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.
摘要翻译：在一个实施例中，系统包括耦合到网络的至少第一节点和第二节点。第二节点包括本地存储器和耦合到本地存储器的直接存储器访问（DMA）控制器。第一节点被配置为将至少第一分组发送到第二节点以访问本地存储器中的数据和至少一个未被编码以访问本地存储器的其他分组。第二节点被配置为从协议栈的数据链路层捕获分组，并且其中DMA控制器被配置为执行与本地存储器的一次或多次传输，以响应于第一分组访问由第一分组指定的数据从数据链路层接收。第二个节点被配置为将另一个分组处理到协议栈的顶部。

5. 发明授权

US07320022B2 System on a chip for caching of data packets based on a cache miss/hit and a state of a control signal 有权
标题翻译：基于高速缓存未命中/缓存和控制信号的状态来缓存数据分组的芯片上的系统
公开(公告)号：US07320022B2
公开(公告)日：2008-01-15
申请号：US10202753
申请日：2002-07-25
申请人： Mark D. Hayter , Shailendra S. Desai , Daniel W. Dobberpuhl , Kwong-Tak A. Chui
发明人： Mark D. Hayter , Shailendra S. Desai , Daniel W. Dobberpuhl , Kwong-Tak A. Chui
IPC分类号： G06F13/00
CPC分类号： H04L47/30 , G06F13/128 , H04L45/00 , H04L45/60 , H04L47/29 , H04L49/103 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901 , H04L49/9042
摘要： A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.
摘要翻译：分组处理系统可以包括集成到单个集成电路中的处理器，高速缓存，存储器控制器和至少一个分组接口电路。在一个实施例中（其可以在集成或非集成系统中使用），分组接口电路被配置为在接收到的分组的一部分的高速缓存中引起分配。在一个实施例中（其可以在集成或非集成系统中使用），存储器控制器可以被配置为选择性地阻止存储器事务。特别地，存储器控制器可以实现至少两个块信号，一个用于分组接口电路，一个用于其他设备。当存储器控制器的输入队列逼近时，块信号可用于控制存储器事务的启动。

6. 发明申请

US20100188980A1 Explicit Flow Control in a Gigabit/10 Gigabit Ethernet System 审中-公开
标题翻译：千兆/万兆以太网系统中的显式流量控制
公开(公告)号：US20100188980A1
公开(公告)日：2010-07-29
申请号：US12753466
申请日：2010-04-02
申请人： Shailendra S. Desai , Mark D. Hayter
发明人： Shailendra S. Desai , Mark D. Hayter
IPC分类号： H04L1/00
CPC分类号： H04L47/245 , H04L47/10 , H04L47/13
摘要： In one embodiment, a system comprises a communication medium; a first controller coupled to the communication medium; and a second controller coupled to the communication medium. The first controller is configured to interrupt transmission of a packet on the communication medium to the second controller subsequent to transmission of a first portion of the packet. The first controller is configured to transmit at least one control symbol on the communication medium in response to interrupting transmission of the packet, and wherein the first controller is configured to continue transmission of the packet with a second portion of the packet. The controller(s) may include, in some embodiments, a media access controller and a physical coding sublayer.
摘要翻译：在一个实施例中，系统包括通信介质; 耦合到所述通信介质的第一控制器; 以及耦合到所述通信介质的第二控制器。第一控制器被配置为在传送分组的第一部分之后中断在通信介质上的分组到第二控制器的传输。第一控制器被配置为响应于中断分组的传输而在通信介质上发送至少一个控制符号，并且其中第一控制器被配置为继续使用分组的第二部分传输分组。在一些实施例中，控制器可以包括媒体访问控制器和物理编码子层。

7. 发明授权

US07287649B2 System on a chip for packet processing 失效
标题翻译：系统在芯片上进行数据包处理
公开(公告)号：US07287649B2
公开(公告)日：2007-10-30
申请号：US09861188
申请日：2001-05-18
申请人： Mark D. Hayter , Shailendra S. Desai , Daniel W. Dobberpuhl , Kwong-Tak A. Chui
发明人： Mark D. Hayter , Shailendra S. Desai , Daniel W. Dobberpuhl , Kwong-Tak A. Chui
IPC分类号： G06F13/00
CPC分类号： H04L47/30 , G06F13/128 , H04L45/00 , H04L45/60 , H04L47/29 , H04L49/103 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901 , H04L49/9042
摘要： A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.
摘要翻译：分组处理系统可以包括集成到单个集成电路中的处理器，高速缓存，存储器控制器和至少一个分组接口电路。在一个实施例中（其可以在集成或非集成系统中使用），分组接口电路被配置为在接收到的分组的一部分的高速缓存中引起分配。在一个实施例中（其可以在集成或非集成系统中使用），存储器控制器可以被配置为选择性地阻止存储器事务。特别地，存储器控制器可以实现至少两个块信号，一个用于分组接口电路，一个用于其他设备。当存储器控制器的输入队列逼近时，块信号可用于控制存储器事务的启动。

8. 发明申请

US20130061003A1 COHERENCE SWITCH FOR I/O TRAFFIC 有权
标题翻译：用于I / O交通的协调开关
公开(公告)号：US20130061003A1
公开(公告)日：2013-03-07
申请号：US13226718
申请日：2011-09-07
申请人： Timothy J. Millet , Muditha Kanchana , Shailendra S. Desai
发明人： Timothy J. Millet , Muditha Kanchana , Shailendra S. Desai
IPC分类号： G06F12/08
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A system, apparatus, and method for routing traffic in a SoC from I/O devices to memory. A coherence switch routes coherent traffic through a coherency port on a processor complex to a real-time port of a memory controller. The coherence switch routes non-coherent traffic to a non-real time port of the memory controller. The coherence switch can also dynamically switch traffic between the two paths. The routing of traffic can be configured via a configuration register, and while software can initiate an update to the configuration register, the actual coherence switch hardware will implement the update. Software can write to a software-writeable copy of the configuration register to initiate an update to the flow path to memory for a transaction identifier. The coherence switch detects the update to the software-writeable copy, and then the coherence switch updates the working copy of the configuration register and implements the new routing.
摘要翻译：用于将SoC中的业务从I / O设备路由到存储器的系统，装置和方法。相干切换器将相干流量通过处理器复合体上的一致端口路由到存储器控制器的实时端口。相干切换将非相干流量路由到存储器控制器的非实时端口。相干切换器还可以动态地切换两条路径之间的流量。流量路由可以通过配置寄存器配置，而软件可以启动对配置寄存器的更新，实际的相干交换机硬件将实现更新。软件可以写入配置寄存器的可写入软件的副本，以启动对事务标识符的存储器流程的更新。相干开关检测到软件可写入副本的更新，然后相干开关更新配置寄存器的工作副本并实现新的路由。

9. 发明授权

US06957290B1 Fast arbitration scheme for a bus 有权
标题翻译：公交快速仲裁方案
公开(公告)号：US06957290B1
公开(公告)日：2005-10-18
申请号：US09684023
申请日：2000-10-06
申请人： Joseph B. Rowlands , David L. Anderson , Shailendra S. Desai
发明人： Joseph B. Rowlands , David L. Anderson , Shailendra S. Desai
IPC分类号： G06F13/00 , G06F13/14 , G06F13/16 , G06F13/368
CPC分类号： G06F13/1652 , G06F13/368
摘要： A distributed arbitration scheme includes arbiters with each agent. The arbiters receive request signals indicating which agents are arbitrating for the bus. Additionally, the agent currently using the bus broadcasts an agent identifier assigned to that agent. The arbiters receive the agent identifier and use the agent identifier as an indication of the winner of the preceding arbitration. Accordingly, the arbiters determine if the corresponding agent wins the arbitration, but may not attempt to calculate which other agent wins the arbitration. In one embodiment, the arbiter maintains a priority state indicative of which of the other agents are higher priority than the corresponding agent and which of the other agents are lower priority. In one implementation, the bus may be a split transaction bus and thus each requesting agent may include an address arbiter and each responding agent may include a data arbiter.
摘要翻译：分布式仲裁方案包括每个代理的仲裁者。仲裁者接收到指示哪些代理正在为总线进行仲裁的请求信号。此外，当前使用总线的代理广播分配给该代理的代理标识符。仲裁者接收代理标识符，并使用代理标识符作为先前仲裁的获胜者的指示。因此，仲裁人确定相应的代理人是否赢得仲裁，但不能尝试计算哪个其他代理人赢得仲裁。在一个实施例中，仲裁者保持指示其他代理中的哪一个比相应代理更高优先级的优先级状态，而其他代理中的哪一个优先级较低。在一个实现中，总线可以是分割事务总线，因此每个请求代理可以包括地址仲裁器，并且每个响应代理可以包括数据仲裁器。

10. 发明授权

US09176913B2 Coherence switch for I/O traffic 有权
标题翻译：用于I / O流量的相干切换
公开(公告)号：US09176913B2
公开(公告)日：2015-11-03
申请号：US13226718
申请日：2011-09-07
申请人： Timothy J. Millet , Muditha Kanchana , Shailendra S. Desai
发明人： Timothy J. Millet , Muditha Kanchana , Shailendra S. Desai
IPC分类号： G06F13/40 , G06F21/00 , G06F13/00
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A system, apparatus, and method for routing traffic in a SoC from I/O devices to memory. A coherence switch routes coherent traffic through a coherency port on a processor complex to a real-time port of a memory controller. The coherence switch routes non-coherent traffic to a non-real time port of the memory controller. The coherence switch can also dynamically switch traffic between the two paths. The routing of traffic can be configured via a configuration register, and while software can initiate an update to the configuration register, the actual coherence switch hardware will implement the update. Software can write to a software-writeable copy of the configuration register to initiate an update to the flow path to memory for a transaction identifier. The coherence switch detects the update to the software-writeable copy, and then the coherence switch updates the working copy of the configuration register and implements the new routing.
摘要翻译：用于将SoC中的业务从I / O设备路由到存储器的系统，装置和方法。相干切换器将相干流量通过处理器复合体上的一致端口路由到存储器控制器的实时端口。相干切换将非相干流量路由到存储器控制器的非实时端口。相干切换器还可以动态地切换两条路径之间的流量。流量路由可以通过配置寄存器配置，而软件可以启动对配置寄存器的更新，实际的相干交换机硬件将实现更新。软件可以写入配置寄存器的可写入软件的副本，以启动对事务标识符的存储器流程的更新。相干开关检测到软件可写入副本的更新，然后相干开关更新配置寄存器的工作副本并实现新的路由。

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