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1. 发明申请

US20070226463A1 PATCHABLE AND/OR PROGRAMMABLE DECODE USING PREDECODE SELECTION 有权
标题翻译：使用预选选择的可编程和/或可编程代码
公开(公告)号：US20070226463A1
公开(公告)日：2007-09-27
申请号：US11277716
申请日：2006-03-28
申请人： Shailender Chaudhry , Paul Caprioli , Quinn Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Quinn Jacobson , Marc Tremblay
IPC分类号： G06F9/40
CPC分类号： G06F9/3836 , G06F9/30196 , G06F9/328 , G06F9/382 , G06F9/3857 , G06F9/3897
摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a configurable predecode mechanism can be employed to select, for respective instruction patterns, between fixed decode and programmable decode paths provided by a processor. In this way, a patchable and/or programmable decode mechanism can be efficiently provided. In some realizations, either (or both) predecode or (and) decode may be configured or reconfigured post-manufacture. In some realizations, either (or both) predecode or (and) decode may be configured at (or about) initialization. In some realizations, either (or both) predecode or (and) decode may be configured at run-time.
摘要翻译：已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。特别地，已经发现，可以采用可配置的预解码机制来针对相应的指令模式在由处理器提供的固定解码和可编程解码路径之间进行选择。以这种方式，可以有效地提供可修补和/或可编程的解码机制。在一些实现中，可以在制造后配置或重新配置（或两者）预解码或（和）解码。在某些实现中，可以在（或约）初始化时配置（或两者）预解码或（和）解码。在某些实现中，可以在运行时配置（或两者）预解码或（和）解码。

2. 发明申请

US20070106888A1 Return address stack recovery in a speculative execution computing apparatus 有权
标题翻译：在推测执行计算设备中返回地址堆栈恢复
公开(公告)号：US20070106888A1
公开(公告)日：2007-05-10
申请号：US11363625
申请日：2006-02-28
申请人： Shailender Chaudhry , Quinn Jacobson , Paul Caprioli , Marc Tremblay
发明人： Shailender Chaudhry , Quinn Jacobson , Paul Caprioli , Marc Tremblay
IPC分类号： G06F15/00
CPC分类号： G06F9/3806 , G06F9/3863 , G06F9/3867
摘要： A technique recovers return address stack (RAS) content and restores alignment of a RAS top-of-stack (TOS) pointer for occurrences of mispredictions due to speculative operation, out-of-order instruction processing, and exception handling. In at least one embodiment of the invention, an apparatus includes a speculative execution processor pipeline, a first structure for maintaining return addresses relative to instruction flow at a first stage of the pipeline, at least a second structure for maintaining return addresses relative to instruction flow at a second stage of the pipeline. The second stage of the pipeline is deeper in the pipeline than the first stage. The apparatus includes circuitry operable to reproduce at least return addresses from the second structure to the first structure.
摘要翻译：一种技术恢复返回地址堆栈（RAS）内容，并恢复RAS堆栈顶部（TOS）指针的对齐，用于由于推测操作，无序指令处理和异常处理引起的错误预测。在本发明的至少一个实施例中，一种装置包括推测执行处理器流水线，用于在流水线的第一阶段保持相对于指令流的返回地址的第一结构，用于维持相对于指令流的返回地址的至少第二结构在管道的第二阶段。管道的第二阶段比第一阶段管道更深。该装置包括可操作以至少将从第二结构返回地址再现到第一结构的电路。

3. 发明申请

US20070006195A1 Method and structure for explicit software control of data speculation 审中-公开
标题翻译：显式软件控制数据推测的方法和结构
公开(公告)号：US20070006195A1
公开(公告)日：2007-01-04
申请号：US11082281
申请日：2005-03-16
申请人： Christof Braun , Quinn Jacobson , Shailender Chaudhry , Marc Tremblay
发明人： Christof Braun , Quinn Jacobson , Shailender Chaudhry , Marc Tremblay
IPC分类号： G06F9/45
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3863
摘要： Explicit software control is used for data speculations. The explicit software control is applied at selected locations in a computer program to provide the benefit of data speculation while eliminating the need for hardware to perform data speculation. A computer-based method first determines, via explicit software control, whether data speculation for an item, a variable, a pointer, an address, etc., is needed. Upon determining that data speculation for the item is needed, the data speculation is performed under explicit software control. Conversely, if the explicit software control determines that data speculation is not needed, e.g., the value of the item typically obtained by execution of a long latency instruction, is available, an original code segment is executed using an actual value of the item.
摘要翻译：显式软件控制用于数据推测。显式软件控制应用于计算机程序中的选定位置，以提供数据推测的优点，同时不需要硬件来执行数据推测。基于计算机的方法首先通过显式软件控制来确定是否需要对项目，变量，指针，地址等的数据推测。在确定需要该项目的数据推测时，数据推测是在明确的软件控制下执行的。相反，如果显式软件控制确定不需要数据推测，例如，通常通过执行长延迟指令获得的项目的值是可用的，则使用该项目的实际值来执行原始代码段。

4. 发明申请

US20060101254A1 Start transactional execution (STE) instruction to support transactional program execution 有权
公开(公告)号：US20060101254A1
公开(公告)日：2006-05-11
申请号：US11296599
申请日：2005-12-06
申请人： Marc Tremblay , Shailender Chaudhry , Quinn Jacobson
发明人： Marc Tremblay , Shailender Chaudhry , Quinn Jacobson
IPC分类号： G06F9/44
CPC分类号： G06F9/528 , G06F9/3004 , G06F9/30087 , G06F9/30116 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857 , Y10S707/99953
摘要： One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.

5. 发明申请

US20050223201A1 Facilitating rapid progress while speculatively executing code in scout mode 审中-公开
标题翻译：在侦察模式下推测执行代码时，促进快速进展
公开(公告)号：US20050223201A1
公开(公告)日：2005-10-06
申请号：US11095644
申请日：2005-03-30
申请人： Marc Tremblay , Shailender Chaudhry , Quinn Jacobson
发明人： Marc Tremblay , Shailender Chaudhry , Quinn Jacobson
IPC分类号： G06F9/00 , G06F9/38
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a processor that facilitates rapid progress while speculatively executing instructions in scout mode. During normal operation, the processor executes instructions in a normal execution mode. Upon encountering a stall condition, the processor executes the instructions in a scout mode, wherein the instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor. While speculatively executing the instructions in scout mode, the processor maintains dependency information for each register indicating whether or not a value in the register depends on an unresolved data-dependency. If an instruction to be executed in scout mode depends on an unresolved data dependency, the processor executes the instruction as a NOOP so that the instruction executes rapidly without tying up computational resources. The processor also propagates dependency information indicating an unresolved data dependency to a destination register for the instruction.
摘要翻译：本发明的一个实施例提供了一种在侦察模式下推测性地执行指令时促进快速进展的处理器。在正常操作期间，处理器以正常执行模式执行指令。在遇到停顿状态时，处理器以侦察模式执行指令，其中推测性地执行指令以预取将来的负载，但是其中结果未被提交到处理器的架构状态。当在侦察模式中推测性地执行指令时，处理器维护每个寄存器的依赖性信息，指示寄存器中的值是否取决于未解决的数据依赖性。如果以侦察模式执行的指令取决于未解决的数据依赖关系，则处理器将该指令执行为NOOP，以使指令快速执行，而不占用计算资源。处理器还将指示未解决的数据依赖关系的依赖信息传播到指令的目的地寄存器。

6. 发明申请

US20050223194A1 Method and structure for explicit software control using scoreboard status information 有权
标题翻译：使用记分牌状态信息显式软件控制的方法和结构
公开(公告)号：US20050223194A1
公开(公告)日：2005-10-06
申请号：US11082282
申请日：2005-03-16
申请人： Marc Tremblay , Shailender Chaudhry , Quinn Jacobson
发明人： Marc Tremblay , Shailender Chaudhry , Quinn Jacobson
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30061 , G06F9/383 , G06F9/3838 , G06F9/3842
摘要： A user is provided with means to sample memory hierarchy via software. This allows a user to enhance memory-level parallelism via software. A status of information needed for execution of a second computer program instruction is read in response to execution of a first computer program instruction. Execution continues with execution of the second computer program instruction upon the status being a first status. Alternatively, a third computer program instruction is executed upon the status being a second status different from the first status. Thus, execution of the first computer program instruction allows control of the memory hierarchy, which in turn give the user control of the memory hierarchy.
摘要翻译：为用户提供了通过软件对存储器层次结构进行抽样的方法。这允许用户通过软件来增强内存级并行性。响应于第一计算机程序指令的执行，读取执行第二计算机程序指令所需的信息的状态。在状态为第一状态时，继续执行第二计算机程序指令。或者，在状态是与第一状态不同的第二状态的情况下执行第三计算机程序指令。因此，第一计算机程序指令的执行允许对存储器层次的控制，这进而使得用户对存储器层级进行控制。

7. 发明申请

US20070271445A1 SELECTIVELY MONITORING STORES TO SUPPORT TRANSACTIONAL PROGRAM EXECUTION 有权
标题翻译：选择监控存储支持交易性计划执行
公开(公告)号：US20070271445A1
公开(公告)日：2007-11-22
申请号：US11832777
申请日：2007-08-02
申请人： Marc Tremblay , Quinn Jacobson , Shailender Chaudhry
发明人： Marc Tremblay , Quinn Jacobson , Shailender Chaudhry
IPC分类号： G06F9/30
CPC分类号： G06F12/0862 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3857 , G06F9/467 , G06F12/0815
摘要： One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.
摘要翻译：本发明的一个实施例提供了一种系统，其选择性地监视存储指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。在交易执行指令块期间遇到存储指令时，系统确定存储指令是监视存储指令还是非监视存储指令。如果存储指令是监视的存储指令，则系统执行存储操作，并存储与存储指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。如果存储指令是不受监视的存储指令，则系统执行存储操作而不存储标记高速缓存行。

8. 发明申请

US20060200632A1 Selectively unmarking load-marked cache lines during transactional program execution 有权
公开(公告)号：US20060200632A1
公开(公告)日：2006-09-07
申请号：US11399049
申请日：2006-04-06
申请人： Marc Tremblay , Quinn Jacobson , Shailender Chaudhry , Mark Moir , Maurice Herlihy
发明人： Marc Tremblay , Quinn Jacobson , Shailender Chaudhry , Mark Moir , Maurice Herlihy
IPC分类号： G06F12/14
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F12/0862
摘要： One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and-start-new-transaction instruction.

9. 发明申请

US20050262301A1 Method and apparatus for delaying interfering accesses from other threads during transactional program execution 审中-公开
标题翻译：用于在事务性程序执行期间延迟来自其他线程的干扰访问的方法和装置
公开(公告)号：US20050262301A1
公开(公告)日：2005-11-24
申请号：US11189591
申请日：2005-07-25
申请人： Quinn Jacobson , Marc Tremblay , Shailender Chaudhry
发明人： Quinn Jacobson , Marc Tremblay , Shailender Chaudhry
IPC分类号： G06F9/46 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F9/3004 , G06F9/30087 , G06F9/30105 , G06F9/30116 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F9/467 , G06F12/0815 , G06F12/0842
摘要： One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.
摘要翻译：本发明的一个实施例提供了一种在事务执行期间有助于延迟来自其他线程的干扰存储器访问的系统。在一个指令块的事务执行期间，系统从另一个线程（或处理器）接收到执行涉及高速缓存线的存储器访问的请求。如果执行高速缓存行上的存储器访问将干扰事务执行，并且如果可以延迟存储器访问，则系统延迟存储器访问并存储用于高速缓存行的复制信息以使得能够复制高速缓存行回到请求线程。在稍后的时间，当内存访问不再干扰事务执行时，系统执行内存访问并将缓存行复制回请求的线程。

10. 发明申请

US20080022082A1 START TRANSACTIONAL EXECUTION (STE) INSTRUCTION TO SUPPORT TRANSACTIONAL PROGRAM EXECUTION 审中-公开
标题翻译：开展交易执行（STE）指导，以支持交易计划执行
公开(公告)号：US20080022082A1
公开(公告)日：2008-01-24
申请号：US11832298
申请日：2007-08-01
申请人： Marc Tremblay , Shailender Chaudhry , Quinn Jacobson
发明人： Marc Tremblay , Shailender Chaudhry , Quinn Jacobson
IPC分类号： G06F9/30
CPC分类号： G06F9/528 , G06F9/3004 , G06F9/30087 , G06F9/30116 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857 , Y10S707/99953
摘要： One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.
摘要翻译：本发明的一个实施例支持开始事务执行（STE）指令的执行，其指示要在事务上执行的指令块的开始。在执行程序期间遇到STE指令时，系统开始按照STE指令执行指令块的事务性执行。在事务执行之前进行的更改不会在事务执行成功完成之前提交到处理器的体系结构状态。

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