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    • 5. 发明授权
    • Method of planarizing integrated circuits with fully recessed isolation
dielectric
    • 使用完全凹陷的隔离电介质平面化集成电路的方法
    • US6008107A
    • 1999-12-28
    • US899394
    • 1997-07-23
    • John M. PierceSung Tae Ahn
    • John M. PierceSung Tae Ahn
    • H01L21/762
    • H01L21/76229Y10S438/959
    • An integrated circuit device is fabricated upon a semi-conductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.
    • 通过首先在晶片的表面上形成停止层,在半导体晶片上制造集成电路器件。 孔通过停止层形成,并且阱形成在开口下方的半导体晶片的半导体材料中。 在装置的表面上形成介电层,其基本上填充阱并覆盖停止层。 然后将电介质层平坦化至基本上停止层的水平。 在阻挡层和半导体器件的表面之间设置PAD氧化物层。 将孔和植入物的常规薄膜氧化进入孔的侧壁进行。 使用研磨机械抛光机进行平面化处理,其中机械抛光机当遇到停止层时具有自停特征。