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1. 发明授权

US06891169B2 Electron beam array write head system and method 失效
标题翻译：电子束阵列写头系统及方法
公开(公告)号：US06891169B2
公开(公告)日：2005-05-10
申请号：US10348658
申请日：2003-01-21
申请人： Scott Josef Bukofsky , Bomy Able Chen , Sara Jennifer Eames , Qiang Wu
发明人： Scott Josef Bukofsky , Bomy Able Chen , Sara Jennifer Eames , Qiang Wu
IPC分类号： H01J37/073 , H01J1/304 , H01J37/305 , H01J37/317 , H01L21/027 , H01J37/30 , H01J29/70 , H01J29/72
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3177 , H01J2237/0635 , H01J2237/30433
摘要： An e-beam system generates a set of massively parallel beams of order of magnitude 1,000 by employing a flash eprom to store calibration data and to receive on/off signals directed through the address system of the memory array, the individual electron sources being mounted above the memory array in a geometric array that tracks the structure of the memory array.
摘要翻译：电子束系统通过使用闪光eprom存储校准数据并且接收通过存储器阵列的地址系统引导的接通/断开信号，生成一组数量级为1000的大规模并行光束，各个电子源被安装在跟踪存储器阵列结构的几何数组中的存储器阵列。

2. 发明授权

US5675185A Semiconductor structure incorporating thin film transistors with undoped cap oxide layers 失效
标题翻译：结合具有未掺杂的帽氧化物层的薄膜晶体管的半导体结构
公开(公告)号：US5675185A
公开(公告)日：1997-10-07
申请号：US537219
申请日：1995-09-29
申请人： Bomy Able Chen , Subhash Balakrishna Kulkarni , Jerome Bret Lasky , Randy William Mann , Edward Joseph Nowak , Werner Alois Rausch , Francis Roger White
发明人： Bomy Able Chen , Subhash Balakrishna Kulkarni , Jerome Bret Lasky , Randy William Mann , Edward Joseph Nowak , Werner Alois Rausch , Francis Roger White
IPC分类号： H01L27/06 , H01L27/11 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/1108 , H01L27/0688 , H01L2924/0002
摘要： An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.
摘要翻译：公开了一种改进的场效应晶体管（FET）结构。它包括第一绝缘体层，其包含延伸穿过该层的至少一个主级螺柱; 设置在绝缘体层上并与每个螺柱的上部区域邻接的未掺杂的帽氧化物层; 设置在未掺杂的帽氧化物层上的初级级薄膜晶体管（TFT）; 以及设置在TFT上的平坦化氧化物层。多个TFT可以垂直堆叠，并连接到其他级别的螺柱和金属互连层。本发明的另一个实施例包括在钨型螺柱的表面上使用保护性界面盖。 FET结构可以用作静态随机存取存储器（SRAM）单元的组件。还公开了相关过程。

3. 发明授权

US5665629A Four transistor SRAM process 失效
标题翻译：四晶体管SRAM工艺
公开(公告)号：US5665629A
公开(公告)日：1997-09-09
申请号：US514016
申请日：1995-08-11
申请人： Bomy Able Chen , Gorden Seth Starkey
发明人： Bomy Able Chen , Gorden Seth Starkey
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/1112
摘要： A SRAM cell with cross-coupled transistors, a pair of transfer gate transistors and a pair of load resistors is manufactured by forming a plurality of field effect transistors in a silicon substrate. In one embodiment, the transistors are formed in an SOI substrate to improve soft-error resistance. An insulator layer is deposited over the source, drain and gate contacts (device contact areas), hole openings are etched into the insulating layer to expose a plurality of device contact areas. A highly resistive layer is patterned to substantially cover and in contact with some selected contact hole openings and device contact areas. A conductive material is deposited into all of the contact hole openings so as to substantially over-fill the contact hole openings and make electrical contact with the device contacts and patterned resistive layer. A planarizing process used to remove the conductive material and the resistive layer outside of the contact holes, thus forming all contact studs with selected studs having integrated resistors. The contact studs are interconnected among themselves and connected to a power bus, a ground, word and bit lines to form the SRAM cell.
摘要翻译：通过在硅衬底中形成多个场效应晶体管来制造具有交叉耦合晶体管的SRAM单元，一对传输栅晶体管和一对负载电阻器。在一个实施例中，晶体管形成在SOI衬底中以改善软错误电阻。在源极，漏极和栅极触点（器件接触区域）上沉积绝缘体层，孔绝缘层中蚀刻出孔开口以露出多个器件接触区域。图案化高电阻层以基本上覆盖并接触一些所选择的接触孔开口和设备接触区域。导电材料沉积到所有接触孔开口中，以便基本上填充接触孔开口并与器件触点和图案化电阻层电接触。用于去除接触孔外部的导电材料和电阻层的平面化处理，从而形成具有集成电阻器的所选螺柱的所有触头螺柱。接触柱在它们之间互连并连接到电源总线，接地，字和位线以形成SRAM单元。

4. 发明授权

US6022766A Semiconductor structure incorporating thin film transistors, and methods for its manufacture 失效
标题翻译：掺入薄膜晶体管的半导体结构及其制造方法
公开(公告)号：US6022766A
公开(公告)日：2000-02-08
申请号：US797904
申请日：1997-02-10
申请人： Bomy Able Chen , Subhash Balakrishna Kulkarni , Jerome Brett Lasky , Randy William Mann , Edward Joseph Nowak , Werner Alois Rausch , Francis Roger White
发明人： Bomy Able Chen , Subhash Balakrishna Kulkarni , Jerome Brett Lasky , Randy William Mann , Edward Joseph Nowak , Werner Alois Rausch , Francis Roger White
IPC分类号： H01L27/06 , H01L27/11 , H01L21/00
CPC分类号： H01L27/1108 , H01L27/0688 , H01L2924/0002
摘要： An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.
摘要翻译：公开了一种改进的场效应晶体管（FET）结构。它包括第一绝缘体层，其包含延伸穿过该层的至少一个主级螺柱; 设置在绝缘体层上并与每个螺柱的上部区域邻接的未掺杂的帽氧化物层; 设置在未掺杂的帽氧化物层上的初级级薄膜晶体管（TFT）; 以及设置在TFT上的平坦化氧化物层。多个TFT可以垂直堆叠，并连接到其他级别的螺柱和金属互连层。本发明的另一个实施例包括在钨型螺柱的表面上使用保护性界面盖。 FET结构可以用作静态随机存取存储器（SRAM）单元的组件。还公开了相关过程。

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