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    • 3. 发明授权
    • Precise position determination using VHF omni-directional radio range signals
    • 使用VHF全向无线电范围信号进行精确位置确定
    • US08179318B1
    • 2012-05-15
    • US12556714
    • 2009-09-10
    • Scott FurmanGuttorm Opshaug
    • Scott FurmanGuttorm Opshaug
    • G01S1/44
    • G01S1/50G01S1/045
    • Apparatus having corresponding methods and computer programs comprise a wireless receiver to receive a Very High Frequency (VHF) Omni-directional Radio Range (VOR) signal comprising a frequency-modulated (FM) component; an analog-to-digital converter to generate a digital signal based on the VOR signal, the digital signal comprising data representing the FM component; and a FM phase circuit comprising a correlator to generate a correlation peak based on the data representing the FM component and an ideal representation of the FM component, and a peak detector to determine a phase of the FM component based on the correlation peak.
    • 具有相应方法和计算机程序的装置包括无线接收器,用于接收包括调频(FM)分量的超高频(VHF)全向无线范围(VOR)信号; 模数转换器,用于基于所述VOR信号产生数字信号,所述数字信号包括表示所述FM分量的数据; 以及FM相电路,包括相关器,用于基于表示FM分量的数据和FM分量的理想表示来生成相关峰;以及峰值检测器,用于基于相关峰确定FM分量的相位。
    • 10. 发明授权
    • System for placing entries of an outstanding processor request into a
free pool after the request is accepted by a corresponding peripheral
device
    • 在请求被相应的外围设备接受之后,将未完成的处理器请求的条目放入空闲池中的系统
    • US5737547A
    • 1998-04-07
    • US480739
    • 1995-06-07
    • William K. ZuravleffMark SemmelmeyerTimothy RobinsonScott Furman
    • William K. ZuravleffMark SemmelmeyerTimothy RobinsonScott Furman
    • G06F9/38G06F13/36G06F9/22
    • G06F9/3824
    • A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.
    • 提供非阻塞负载缓冲器用于高速微处理器和存储器系统。 非阻塞负载缓冲器将高速处理器/高速缓存总线接口,该总线将处理器和高速缓存连接到非阻塞负载缓冲区,其中低速外设总线连接到外围设备。 非阻塞负载缓冲器允许以相对较低带宽的外围设备从外围设备的最大速率直接从处理器的编程I / O检索数据,从而可以处理和存储数据,而不会使处理器无需空闲。 可以同时缓冲多处理器内的多个处理器的I / O请求,以便可以在设备的等待时间期间处理多个非阻塞负载。 因此,通过处理器的编程I / O实现来自多个I / O设备的连续最大吞吐量,并且可以减少完成任务和处理数据所需的时间。 此外,提供了多重优先级的非阻塞负载缓冲器,用于通过基于优先级的存储器和外设访问调度来服务运行不同期限的实时处理的多处理器。