专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06372559B1 Method for self-aligned vertical double-gate MOSFET 失效
标题翻译：自对准垂直双栅极MOSFET的方法
公开(公告)号：US06372559B1
公开(公告)日：2002-04-16
申请号：US09709073
申请日：2000-11-09
申请人： Scott Crowder , Michael J. Hargrove , Suk Hoon Ku , L. Ronald Logan
发明人： Scott Crowder , Michael J. Hargrove , Suk Hoon Ku , L. Ronald Logan
IPC分类号： H01L2100
CPC分类号： H01L29/78696 , H01L21/823885 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/78642 , H01L29/78648
摘要： A method of forming a self-aligned vertical double-gate metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes processing steps that are CMOS compatible. The method include the steps of growing an oxide layer on a surface of a silicon-on-insulator (SOI) substrate, said SOI substrate having a buried oxide region located between a top Si-containing layer and a bottom Si-containing layer, wherein said top and bottom Si-containing layers are of the same conductivity-type; patterning and etching gate openings in said oxide layer, said top Si-containing layer and said buried oxide region stopping on said bottom Si-containing layer of said SOI substrate; forming a gate dielectric on exposed vertical sidewalls of said gate openings and filling said gate openings with silicon; removing oxide on horizontal surfaces which interface with said Si-containing bottom layer; recrystallizing silicon interfaced to said gate dielectric and filling said gate openings with expitaxial silicon; forming a mask on said oxide layer so as cover one of the silicon filled gate openings, while leaving an adjacent silicon filled gate opening exposed; selectively implanting dopants of said first conductivity-type into said exposed silicon filled gate opening and activating the same, wherein said dopants are implanted at an ion dosage of about 1E15 cm−2 or greater; selectively etching the exposed oxide layer and the underlying top Si-containing layer of said SOI substrate stopping on said buried oxide layer; removing said mask and implanting a graded-channel dopant profile in said previously covered silicon filled gate opening; etching any remaining oxide layer and forming spacers about said silicon filled gate openings; and saliciding any exposed silicon surfaces.
摘要翻译：提供了一种形成自对准垂直双栅极金属氧化物半导体场效应晶体管（MOSFET）器件的方法，其包括与CMOS兼容的处理步骤。该方法包括以下步骤：在绝缘体上硅（SOI）衬底的表面上生长氧化物层，所述SOI衬底具有位于顶部含Si层和底部含Si层之间的掩埋氧化物区域，其中所述顶部和底部含Si层具有相同的导电型; 在所述氧化物层中图案化和蚀刻栅极开口，所述顶部含Si层和所述掩埋氧化物区停止在所述SOI衬底的所述底部含Si层上; 在所述栅极开口的暴露的垂直侧壁上形成栅极电介质，并用硅填充所述栅极开口; 在与所述含Si底层相接的水平表面上去除氧化物; 与所述栅介质接合的再结晶硅，并用外延硅填充所述栅极开口; 在所述氧化物层上形成掩模，以便覆盖硅填充的栅极开口中的一个，同时使相邻的硅填充的栅极开口暴露; 将所述第一导电类型的掺杂剂选择性地注入到所述暴露的硅填充的栅极开口中并使其激活，其中所述掺杂剂以约1E15cm-2或更大的离子剂量注入; 选择性地蚀刻暴露的氧化物层和停留在所述掩埋氧化物层上的所述SOI衬底的下层顶部含Si层; 去除所述掩模并在所述预先覆盖的硅填充的开口中注入分级沟道掺杂物分布; 蚀刻任何剩余的氧化物层并围绕所述硅填充的栅极开口形成间隔物; 并暴露任何硅表面。

IPRDB

热门服务

关于我们

友情链接

联系方式