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1. 发明申请

US20110147764A1 TRANSISTORS WITH A DIELECTRIC CHANNEL DEPLETION LAYER AND RELATED FABRICATION METHODS 审中-公开
标题翻译：具有介质通道层的晶体管及相关制造方法
公开(公告)号：US20110147764A1
公开(公告)日：2011-06-23
申请号：US12612499
申请日：2009-11-04
申请人： Sarit Dhar , Sei-Hyung Ryu , Veena Misra , Daniel J. Lichtenwalner
发明人： Sarit Dhar , Sei-Hyung Ryu , Veena Misra , Daniel J. Lichtenwalner
IPC分类号： H01L29/78 , H01L21/28 , H01L21/265
CPC分类号： H01L29/66068 , H01L29/51 , H01L29/78
摘要： A metal-insulator-semiconductor field-effect transistor (MISFET) includes a semiconductor layer with source and drain regions of a first conductivity type spaced apart therein. A channel region of a first conductivity type extends between the source and drain regions. A gate contact is on the channel region. A dielectric channel depletion layer is between the gate contact and the channel region. The dielectric channel depletion layer provides a net charge having the same polarity as the first conductivity type charge carriers, and which may deplete the first conductivity type charge carriers from an adjacent portion of the channel region when no voltage is applied to the gate contact.
摘要翻译：金属 - 绝缘体 - 半导体场效应晶体管（MISFET）包括具有间隔开的第一导电类型的源区和漏区的半导体层。第一导电类型的沟道区域在源区和漏区之间延伸。通道区域上有一个门接点。电介质沟道耗尽层在栅极接触和沟道区之间。电介质通道耗尽层提供具有与第一导电类型电荷载流子相同极性的净电荷，并且当没有电压施加到栅极接触时，可以从沟道区的相邻部分消耗第一导电型电荷载流子。

2. 发明授权

US07312100B2 In situ patterning of electrolyte for molecular information storage devices 有权
标题翻译：用于分子信息存储设备的电解质原位图案化
公开(公告)号：US07312100B2
公开(公告)日：2007-12-25
申请号：US10837028
申请日：2004-04-30
申请人： David F. Bocian , Werner G. Kuhr , Jonathan S. Lindsey , Veena Misra
发明人： David F. Bocian , Werner G. Kuhr , Jonathan S. Lindsey , Veena Misra
IPC分类号： H01L51/40
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0009 , H01L51/0021 , H01L51/005 , H01L51/0077 , H01L51/0595 , Y10S977/896 , Y10S977/943
摘要： This invention pertains to methods assembly of organic molecules and electrolytes in hybrid electronic. In one embodiment, a method is provided that involves contacting a surface/electrode with a compound of formula: R-L2-M-L1-Z1 where Z1 is a surface attachment group; L1 and L2 are independently linker or covalent bonds; M is an information storage molecule; and R is a protected or unprotected reactive site or group; where the contacting results in attachment of the redox-active moiety to the surface via the surface attachment group; and ii) contacting the surface-attached information storage molecule with an electrolyte having the formula: J-Q where J is a charged moiety (e.g., an electrolyte); and Q is a reactive group that is reactive with the reactive group (R) and attaches J to the information storage molecule thereby patterning the electrolyte on the surface.
摘要翻译：本发明涉及混合电子中有机分子和电解质的组装方法。在一个实施方案中，提供了一种方法，其涉及使表面/电极与下式化合物接触：RL 2 -ML 1 -Z 1 / 其中Z 1是表面附着基团; L 1和L 2独立地是连接基或共价键; M是信息存储分子; 并且R是被保护或未被保护的反应性位点或基团; 其中所述接触导致通过所述表面附着基团将所述氧化还原活性部分附着到所述表面; 和ii）使表面附着的信息存储分子与具有下式的电解质接触：J-Q其中J是带电部分（例如电解质）; 并且Q是与反应性基团（R）反应并且将J附着到信息存储分子的反应性基团，从而对表面上的电解质进行图案化。

3. 发明申请

US20070212897A1 HIGH-TEMPERATURE ATTACHMENT OF ORGANIC MOLECULES TO SUBSTRATES 失效
标题翻译：有机分子与基底的高温连接
公开(公告)号：US20070212897A1
公开(公告)日：2007-09-13
申请号：US11688194
申请日：2007-03-19
申请人： David Bocian , Jonathan Lindsey , Zhiming Liu , Amir Yasseri , Veena Misra , Qian Zhao , Qiliang Li , Shyam Surthi , Robert Loewe
发明人： David Bocian , Jonathan Lindsey , Zhiming Liu , Amir Yasseri , Veena Misra , Qian Zhao , Qiliang Li , Shyam Surthi , Robert Loewe
IPC分类号： H01L21/469
CPC分类号： H01L51/0002 , B82Y10/00 , G11B9/14 , G11B9/149 , G11C13/0014 , G11C13/0016 , H01L51/0008 , H01L51/001 , H01L51/0026 , H01L51/0075 , H01L51/0077 , H01L51/0595 , H01L51/4213 , H01M4/60 , H01M14/005 , Y02E10/549
摘要： This invention provides a new procedure for attaching molecules to semiconductor surfaces, in particular silicon. The molecules, which include, but are not limited to porphyrins and ferrocenes, have been previously shown to be attractive candidates for molecular-based information storage. The new attachment procedure is simple, can be completed in short times, requires minimal amounts of material, is compatible with diverse molecular functional groups, and in some instances affords unprecedented attachment motifs. These features greatly enhance the integration of the molecular materials into the processing steps that are needed to create hybrid molecular/semiconductor information storage devices.
摘要翻译：本发明提供了一种将分子连接到半导体表面，特别是硅的新方法。以前已经显示出包括但不限于卟啉和二茂铁的分子是用于基于分子的信息存储的有吸引力的候选物。新的附件程序简单，可以在短时间内完成，需要最少量的材料，与不同的分子官能团相容，并在某些情况下提供前所未有的附着图案。这些特征大大增强了分子材料与创建混合分子/半导体信息存储设备所需的处理步骤的集成。

4. 发明授权

US07253466B2 Crossbar array microelectronic electrochemical cells 失效
标题翻译：交叉阵列微电子电化学电池
公开(公告)号：US07253466B2
公开(公告)日：2007-08-07
申请号：US11166938
申请日：2005-06-24
申请人： Veena Misra , John Damiano, Jr.
发明人： Veena Misra , John Damiano, Jr.
IPC分类号： H01L29/76
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , G11C13/02 , G11C2213/77 , Y10T29/49108 , Y10T29/49115
摘要： The present invention provides microelectronic electrochemical structures and related fabrication methods. A composite microelectronic structure is provided that includes first and second conductors dielectrically isolated from one another at a crossing thereof, the crossing surrounded by a dielectric material. A portion of the dielectric material around the crossing of the first and second conductors is removed to form a well that exposes respective outer surfaces of the first and second conductors and a molecule is deposited in the well such that the deposited molecule contacts the exposed outer surfaces of the first and second conductors.
摘要翻译：本发明提供微电子电化学结构和相关制造方法。提供了复合微电子结构，其包括在其交叉处彼此介电隔离的第一和第二导体，所述交叉被电介质材料包围。除去第一和第二导体的交叉点周围的电介质材料的一部分以形成露出第一和第二导体的相应外表面的阱，并且分子沉积在阱中，使得沉积的分子接触暴露的外表面的第一和第二导体。

5. 发明申请

US20050062097A1 Method and system for molecular charge storage field effect transistor 审中-公开
标题翻译：分子电荷存储场效应晶体管的方法和系统
公开(公告)号：US20050062097A1
公开(公告)日：2005-03-24
申请号：US10498743
申请日：2002-12-12
申请人： Veena Misra , David Bocian , Werner Kuhr , Jonathan Lindsey
发明人： Veena Misra , David Bocian , Werner Kuhr , Jonathan Lindsey
IPC分类号： H01L21/8247 , G11C11/56 , G11C13/02 , H01L27/115 , H01L27/28 , H01L29/788 , H01L29/792 , H01L51/05
CPC分类号： H01L27/283 , B82Y10/00 , G11C11/5664 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C2213/53 , H01L51/052 , H01L51/0529 , Y10S977/721 , Y10S977/887 , Y10S977/937
摘要： A method and/or system and/or apparatus for a molecular-based FET device (an m-FET) uses charge storing molecules (120) between a gate (110) and channel (105) of an FET-type transistor. Further embodiments describe fabrication methods for using combinations of standard practices in lithography and synthetic chemistry and novel elements.
摘要翻译：用于分子型FET器件（m-FET）的方法和/或系统和/或设备在FET型晶体管的栅极（110）和沟道（105）之间使用电荷存储分子（120）。另外的实施例描述了使用光刻和合成化学中的标准实践的组合以及新颖元件的制造方法。

6. 发明授权

US08529996B2 High-temperature attachment of organic molecules to substrates 失效
标题翻译：将有机分子高温附着于底物
公开(公告)号：US08529996B2
公开(公告)日：2013-09-10
申请号：US11688194
申请日：2007-03-19
申请人： David F. Bocian , Jonathan S. Lindsey , Zhiming Liu , Amir A. Yasseri , Veena Misra , Qian Zhao , Qiliang Li , Shyam Surthi , Robert S. Loewe
发明人： David F. Bocian , Jonathan S. Lindsey , Zhiming Liu , Amir A. Yasseri , Veena Misra , Qian Zhao , Qiliang Li , Shyam Surthi , Robert S. Loewe
IPC分类号： C23C16/00
CPC分类号： H01L51/0002 , B82Y10/00 , G11B9/14 , G11B9/149 , G11C13/0014 , G11C13/0016 , H01L51/0008 , H01L51/001 , H01L51/0026 , H01L51/0075 , H01L51/0077 , H01L51/0595 , H01L51/4213 , H01M4/60 , H01M14/005 , Y02E10/549
摘要： This invention provides a new procedure for attaching molecules to semiconductor surfaces, in particular silicon. The molecules, which include, but are not limited to porphyrins and ferrocenes, have been previously shown to be attractive candidates for molecular-based information storage. The new attachment procedure is simple, can be completed in short times, requires minimal amounts of material, is compatible with diverse molecular functional groups, and in some instances affords unprecedented attachment motifs. These features greatly enhance the integration of the molecular materials into the processing steps that are needed to create hybrid molecular/semiconductor information storage devices.
摘要翻译：本发明提供了一种将分子连接到半导体表面，特别是硅的新方法。以前已经显示出包括但不限于卟啉和二茂铁的分子是用于基于分子的信息存储的有吸引力的候选物。新的附件程序简单，可以在短时间内完成，需要最少量的材料，与不同的分子官能团相容，并在某些情况下提供前所未有的附着图案。这些特征大大增强了分子材料与创建混合分子/半导体信息存储设备所需的处理步骤的集成。

7. 发明授权

US07265375B2 Optoelectonic devices having arrays of quantum-dot compound semiconductor superlattices therein 有权
标题翻译：具有量子点化合物半导体超晶格阵列的光电器件
公开(公告)号：US07265375B2
公开(公告)日：2007-09-04
申请号：US11065085
申请日：2005-02-24
申请人： Zhibo Zhang , Veena Misra , Salah M. A. Bedair , Mehmet Ozturk
发明人： Zhibo Zhang , Veena Misra , Salah M. A. Bedair , Mehmet Ozturk
IPC分类号： H01L29/12
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02381 , H01L21/02395 , H01L21/02463 , H01L21/02488 , H01L21/02546 , H01L21/0262 , H01L21/02642 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/125 , H01L29/127 , Y10S977/762
摘要： Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.
摘要翻译：形成纳米级电子和光电子器件的方法包括在其中形成其中具有半导体层的衬底和在半导体层上的衬底绝缘层。在衬底绝缘层上形成具有非光刻限定的纳米通道的第一阵列的蚀刻模板。该蚀刻模板可以包括阳极氧化的金属氧化物，例如阳极氧化的氧化铝（AAO）薄膜。然后选择性地蚀刻衬底绝缘层以在其中限定纳米通道的第二阵列。该选择蚀刻步骤优选使用蚀刻模板作为蚀刻掩模，将第一纳米通道阵列转移到下面的衬底绝缘层，其可以比蚀刻模板更薄。然后在第二纳米通道阵列中形成半导体纳米柱阵列。阵列中的半导体纳米柱可以具有在约8nm和约50nm之间的范围内的平均直径。半导体纳米柱也优选与半导体层同质外延或异质外延。

8. 发明申请

US20050207208A1 Situ patterning of electrolyte for molecular information storage devices 有权
标题翻译：用于分子信息存储设备的电解质的原位图案化
公开(公告)号：US20050207208A1
公开(公告)日：2005-09-22
申请号：US10837028
申请日：2004-04-30
申请人： David Bocian , Werner Kuhr , Jonathan Lindsey , Veena Misra
发明人： David Bocian , Werner Kuhr , Jonathan Lindsey , Veena Misra
IPC分类号： G11C11/00 , G11C13/00 , G11C13/02 , H01L20060101 , H01L51/00 , H01L51/30 , H01M6/14 , H01M6/16 , H01M6/18
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0009 , H01L51/0021 , H01L51/005 , H01L51/0077 , H01L51/0595 , Y10S977/896 , Y10S977/943
摘要： This invention pertains to methods assembly of organic molecules and electrolytes in hybrid electronic. In one embodiment, a is provided that involves contacting a surface/electrode with a compound if formula: R-L2-M-L1-Z1 where Z1 is a surface attachment group; L1 and L2 are independently linker or covalent bonds; M is an information storage molecule; and R is a protected or unprotected reactive site or group; where the contacting results in attachment of the redox-active moiety to the surface via the surface attachment group; and ii) contacting the surface-attached information storage molecule with an electrolyte having the formula: J-Q where J is a charged moiety (e.g., an electrolyte); and Q is a reactive group that is reactive with the reactive group (R) and attaches J to the information storage molecule thereby patterning the electrolyte on the surface.
摘要翻译：本发明涉及混合电子中有机分子和电解质的组装方法。在一个实施方案中，提供了一种方法，其包括使表面/电极与化合物接触，如果下列公式：RL 2 -ML 1 -Z 1 / Z 1是表面附着基团; L 1和L 2独立地是连接基或共价键; M是信息存储分子; 并且R是被保护或未被保护的反应性位点或基团; 其中所述接触导致通过所述表面附着基团将所述氧化还原活性部分附着到所述表面; 和ii）使表面附着的信息存储分子与具有下式的电解质接触：J-Q其中J是带电部分（例如电解质）; 并且Q是与反应性基团（R）反应并且将J附着到信息存储分子的反应性基团，从而对表面上的电解质进行图案化。

9. 发明授权

US06709929B2 Methods of forming nano-scale electronic and optoelectronic devices using non-photolithographically defined nano-channel templates 失效
标题翻译：使用非光刻定义的纳米通道模板形成纳米级电子和光电器件的方法
公开(公告)号：US06709929B2
公开(公告)日：2004-03-23
申请号：US10178941
申请日：2002-06-24
申请人： Zhibo Zhang , Veena Misra , Salah M. A. Bedair , Mehmet Ozturk
发明人： Zhibo Zhang , Veena Misra , Salah M. A. Bedair , Mehmet Ozturk
IPC分类号： H01L21336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02381 , H01L21/02395 , H01L21/02463 , H01L21/02488 , H01L21/02546 , H01L21/0262 , H01L21/02642 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/125 , H01L29/127 , Y10S977/762
摘要： Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.
摘要翻译：形成纳米级电子和光电子器件的方法包括在其中形成其中具有半导体层的衬底和在半导体层上的衬底绝缘层。在衬底绝缘层上形成具有非光刻限定的纳米通道的第一阵列的蚀刻模板。该蚀刻模板可以包括阳极氧化的金属氧化物，例如阳极氧化的氧化铝（AAO）薄膜。然后选择性地蚀刻衬底绝缘层以在其中限定纳米通道的第二阵列。该选择蚀刻步骤优选使用蚀刻模板作为蚀刻掩模，将第一纳米通道阵列转移到下面的衬底绝缘层，其可以比蚀刻模板更薄。然后在第二纳米通道阵列中形成半导体纳米柱阵列。阵列中的半导体纳米柱可以具有在约8nm和约50nm之间的范围内的平均直径。半导体纳米柱也优选与半导体层同质外延或异质外延。

10. 发明授权

US5960270A Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions 失效
标题翻译：用于形成具有在形成自对准源区和漏区之后形成的金属栅电极的MOS晶体管的方法
公开(公告)号：US5960270A
公开(公告)日：1999-09-28
申请号：US907990
申请日：1997-08-11
申请人： Veena Misra , Suresh Venkatesan , Christopher C. Hobbs , Brad Smith , Jeffrey S. Cope , Earnest B. Wilson
发明人： Veena Misra , Suresh Venkatesan , Christopher C. Hobbs , Brad Smith , Jeffrey S. Cope , Earnest B. Wilson
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/768 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66583 , H01L21/2257 , H01L21/28114 , H01L29/42376 , H01L29/66553 , H01L29/66606 , H01L21/76807 , H01L29/4958 , H01L29/4966 , H01L29/4975 , H01L29/66537 , H01L29/66545 , H01L29/66575 , H01L29/6659 , H01L29/7833
摘要： A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.
摘要翻译：用于形成金属栅极MOS晶体管的方法开始于在衬底（12或102）内形成源极和漏极（26,28和/或118）。这些源极和漏极区域（26,28和118）与光刻图案特征（24或108）自对准。在形成源极和漏极区之后，特征（24和108）被处理以用金属栅极层（28a或128a）填充这些特征，然后将该金属层（28a或128a）化学机械抛光（CMPed）以形成在特征（24或108）内的金属插塞区域（28b或128b），插塞区域（28b或128b）以镶嵌或双重嵌入方式形成，其中该金属插塞区域（28b或128b）是自对准的到先前形成的源极和漏极区，并且优选地用作金属MOS栅极区。

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