专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090253254A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090253254A1
公开(公告)日：2009-10-08
申请号：US12336487
申请日：2008-12-16
申请人： Sang-Hoon PARK , Yun-Seok CHO , Sang-Hoon CHO , Chun-Hee LEE
发明人： Sang-Hoon PARK , Yun-Seok CHO , Sang-Hoon CHO , Chun-Hee LEE
IPC分类号： H01L21/28
CPC分类号： H01L21/823487 , H01L21/0334 , H01L21/32139 , H01L21/823437 , H01L29/66666 , H01L29/7827
摘要： In a method of fabricating a semiconductor device having vertical channels and a method of patterning a gate electrode of such semiconductor device, an initial conductive layer is removed by multiple etching processes.
摘要翻译：在制造具有垂直沟道的半导体器件的方法和对这种半导体器件的栅电极进行构图的方法中，通过多次蚀刻工艺去除初始导电层。

2. 发明申请

US20110169074A1 VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：垂直通道晶体管及其制造方法
公开(公告)号：US20110169074A1
公开(公告)日：2011-07-14
申请号：US13071182
申请日：2011-03-24
申请人： Chun-Hee LEE
发明人： Chun-Hee LEE
IPC分类号： H01L27/088
CPC分类号： H01L29/7827 , H01L29/66666
摘要： A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.
摘要翻译：垂直沟道晶体管包括从衬底的顶表面垂直于上部延伸的多个有源柱图案。栅极绝缘层沉积在有源柱图案的侧壁上，并且用作柱状图案和周围的下部栅电极之间的离子扩散阻挡层。得到的柱状图案结构用金属包封。所得柱状图案通过旋涂介质（SOD）的牺牲层在所有侧面被指定的高度包围。金属层被蚀刻回到牺牲层的高度，从而形成下部栅电极。绝缘材料的间隔层沉积在柱状图案的上部周围，去除暴露一部分下部栅电极的牺牲层。蚀刻暴露的栅电极以促进半导体集成。

3. 发明申请

US20070114205A1 METHOD OF FORMING ETCHING MASK 失效
标题翻译：形成蚀刻掩模的方法
公开(公告)号：US20070114205A1
公开(公告)日：2007-05-24
申请号：US11556127
申请日：2006-11-02
申请人： Gi-Chung KWON , Nae-Eung LEE , Chang-Ki PARK , Chun-Hee LEE , Duck-Ho KIM
发明人： Gi-Chung KWON , Nae-Eung LEE , Chang-Ki PARK , Chun-Hee LEE , Duck-Ho KIM
IPC分类号： C23F1/00 , H01L21/461 , B44C1/22 , H01L21/302
CPC分类号： H01L21/31116 , G03F7/11 , G03F7/40 , G03F7/405 , H01L21/0273 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L21/31144 , H01L21/32139
摘要： The present invention relates to a method of forming an etching mask. According to the present invention, there is provided a method of forming an etching mask, comprising the steps of: depositing a hard mask film containing silicon on a substrate; depositing a photoresist on the hard mask film; patterning the photoresist; and etching the hard mask film using the photoresist pattern as an mask and using an etching gas including a CHxFy(x, y=1, 2, 3) gas. At this time, an etch selectivity of the hard mask film to the photoresist pattern can be increased using a mixed gas including CH2F2 and H2 gases when etching the hard mask film under the photoresist pattern used in a wavelength of 193 nm or less.
摘要翻译：本发明涉及一种形成蚀刻掩模的方法。根据本发明，提供一种形成蚀刻掩模的方法，包括以下步骤：在衬底上沉积含有硅的硬掩模膜; 在硬掩模膜上沉积光致抗蚀剂; 图案化光刻胶; 并使用光致抗蚀剂图案作为掩模蚀刻硬掩模膜，并使用包含CH 2 x N x（x，y = 1,2,3）气体的蚀刻气体。此时，可以使用包括CH 2 2 H 2 H 2和H 2 O 2的混合气体来增加硬掩模膜对光致抗蚀剂图案的蚀刻选择性，在193nm以下的波长下使用的光致抗蚀剂图案上刻蚀硬掩模膜时，

4. 发明申请

US20090163006A1 METHOD FOR FABRICATING VERTICAL CHANNEL TRANSISTOR 有权
标题翻译：用于制作垂直通道晶体管的方法
公开(公告)号：US20090163006A1
公开(公告)日：2009-06-25
申请号：US12163257
申请日：2008-06-27
申请人： Chun-Hee LEE
发明人： Chun-Hee LEE
IPC分类号： H01L21/306
CPC分类号： H01L29/66666 , H01L27/10876 , H01L29/7827
摘要： A method for fabricating a vertical channel transistor includes forming a structure including a plurality of trimmed pillar patterns, forming a conductive layer for a gate electrode including a seam over a resultant structure with the pillar patterns, performing an etch-back process until the seam is exposed, and forming a gate electrode by etching the etch-backed conductive layer.
摘要翻译：一种用于制造垂直沟道晶体管的方法，包括形成包括多个修整的柱状图案的结构，形成用于栅电极的导电层，该导电层包括在具有柱状图案的合成结构上的接缝，执行回蚀工艺直到接缝为暴露并通过蚀刻蚀刻背衬的导电层形成栅电极。

5. 发明申请

US20090159964A1 VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：垂直通道晶体管及其制造方法
公开(公告)号：US20090159964A1
公开(公告)日：2009-06-25
申请号：US12336474
申请日：2008-12-16
申请人： Chun-Hee LEE
发明人： Chun-Hee LEE
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L29/66666
摘要： A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.
摘要翻译：垂直沟道晶体管包括从衬底的顶表面垂直于上部延伸的多个有源柱图案。栅极绝缘层沉积在有源柱图案的侧壁上，并且用作柱状图案和周围的下部栅电极之间的离子扩散阻挡层。得到的柱状图案结构用金属包封。所得柱状图案通过旋涂介质（SOD）的牺牲层在所有侧面被指定的高度包围。金属层被蚀刻回到牺牲层的高度，从而形成下部栅电极。绝缘材料的间隔层沉积在柱状图案的上部周围，去除暴露一部分下部栅电极的牺牲层。蚀刻暴露的栅电极以促进半导体集成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式