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1. 发明授权

US07884636B2 Single event transient mitigation and measurement in integrated circuits 有权
标题翻译：集成电路中的单事件瞬态缓解和测量
公开(公告)号：US07884636B2
公开(公告)日：2011-02-08
申请号：US12828821
申请日：2010-07-01
申请人： Sana Rezgui , John McCollum , Jih-Jong Wang
发明人： Sana Rezgui , John McCollum , Jih-Jong Wang
IPC分类号： H03K17/16
CPC分类号： H03K19/00392 , H03K19/177
摘要： A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.
摘要翻译：描述了集成电路装置中的单事件瞬态滤波的方法。该装置包括三个顺序元件，每个元件具有数据输入和数据输出，其中三个数据输出中的每一个耦合到投票口的三个输入之一。该方法包括在第一和第二SET域中产生第一和第二名义上等效的逻辑信号，将第一和第二名义上等效的逻辑信号转换成第一，第二和第三名义上等效的数据信道，以及发送第一，第二和第三名义上等效的数据信道到第一，第二和第三顺序元件的数据输入。

2. 发明申请

US20100325598A1 SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS 有权
标题翻译：集成电路中的单次事件瞬态缓解和测量
公开(公告)号：US20100325598A1
公开(公告)日：2010-12-23
申请号：US12828821
申请日：2010-07-01
申请人： Sana Rezgui , John McCollum , Jih-Jong Wang
发明人： Sana Rezgui , John McCollum , Jih-Jong Wang
IPC分类号： G06F17/50
CPC分类号： H03K19/00392 , H03K19/177
摘要： A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.
摘要翻译：描述了集成电路装置中的单事件瞬态滤波的方法。该装置包括三个顺序元件，每个元件具有数据输入和数据输出，其中三个数据输出中的每一个耦合到投票口的三个输入之一。该方法包括在第一和第二SET域中产生第一和第二名义上等效的逻辑信号，将第一和第二名义上等效的逻辑信号转换成第一，第二和第三名义上等效的数据信道，以及发送第一，第二和第三名义上等效的数据信道到第一，第二和第三顺序元件的数据输入。

3. 发明申请

US20090189634A1 SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS 有权
标题翻译：集成电路中的单次事件瞬态缓解和测量
公开(公告)号：US20090189634A1
公开(公告)日：2009-07-30
申请号：US12352512
申请日：2009-01-12
申请人： Sana Rezgui , John McCollum , Jih-Jong Wang
发明人： Sana Rezgui , John McCollum , Jih-Jong Wang
IPC分类号： H03K19/003 , H03K19/177
CPC分类号： H03K19/00392 , H03K19/177
摘要： A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.
摘要翻译：描述了集成电路装置中的单事件瞬态滤波的方法。该装置包括三个顺序元件，每个元件具有数据输入和数据输出，其中三个数据输出中的每一个耦合到投票口的三个输入之一。该方法包括在第一和第二SET域中产生第一和第二名义上等效的逻辑信号，将第一和第二名义上等效的逻辑信号转换成第一，第二和第三名义上等效的数据信道，以及发送第一，第二和第三名义上等效的数据信道到第一，第二和第三顺序元件的数据输入。

4. 发明授权

US07772874B2 Single event transient mitigation and measurement in integrated circuits 有权
标题翻译：集成电路中的单事件瞬态缓解和测量
公开(公告)号：US07772874B2
公开(公告)日：2010-08-10
申请号：US12352512
申请日：2009-01-12
申请人： Sana Rezgui , John McCollum , Jih-Jong Wang
发明人： Sana Rezgui , John McCollum , Jih-Jong Wang
IPC分类号： H03K17/16
CPC分类号： H03K19/00392 , H03K19/177
摘要： A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.
摘要翻译：描述了集成电路装置中的单事件瞬态滤波的方法。该装置包括三个顺序元件，每个元件具有数据输入和数据输出，其中三个数据输出中的每一个耦合到投票口的三个输入之一。该方法包括在第一和第二SET域中产生第一和第二名义上等效的逻辑信号，将第一和第二名义上等效的逻辑信号转换成第一，第二和第三名义上等效的数据信道，以及发送第一，第二和第三名义上等效的数据信道到第一，第二和第三顺序元件的数据输入。

5. 发明申请

US20130264863A1 BREAK-AWAY SWITCH ACTUATED TRAILER LIGHTING AND BRAKING SYSTEM 审中-公开
标题翻译：断开开关动作拖拉机照明和制动系统
公开(公告)号：US20130264863A1
公开(公告)日：2013-10-10
申请号：US13442521
申请日：2012-04-09
申请人： John McCollum
发明人： John McCollum
IPC分类号： B60Q11/00
CPC分类号： B60Q11/00 , B60Q1/305 , B60Q1/46 , B60T7/20 , B60T17/22
摘要： A system for operating alarm features of a trailer towed by a tractor in the event of unintended decoupling of the trailer from the tractor. The system may include a breakaway switch or its functional equivalent, a flasher, and a source of emergency power such as a battery. The output of the system may operate only lights though the flasher, or optionally, also at least one electric brake of the trailer. Where braking is provided, the supply of electrical power is uninterrupted as by the flasher. Importantly, an anti-feedback feature prevents unintended operation of the lights and brake due to back-feeding from the electrical system of the tractor under ordinary operating conditions.
摘要翻译：如果拖车与拖拉机意外脱钩，则用于操作由拖拉机牵引的拖车的警报功能的系统。该系统可以包括分离开关或其功能等效物，闪光器和诸如电池的应急电源。系统的输出可以仅通过闪光灯或者可选地还可以是拖车的至少一个电动制动器操作灯。在提供制动的情况下，电源的供电与闪光灯不间断。重要的是，反馈功能可防止由于在正常操作条件下从拖拉机的电气系统进行反馈而引起的灯和制动器的意外操作。

6. 发明申请

US20110001115A1 RESISTIVE RAM DEVICES FOR PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：用于可编程逻辑器件的电阻RAM器件
公开(公告)号：US20110001115A1
公开(公告)日：2011-01-06
申请号：US12829300
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L45/00
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

7. 发明授权

US07538598B1 Circuit and method for supplying programming potential at voltages larger than BVDss of programming transistors 有权
标题翻译：用于在大于编程晶体管的BVDss的电压下提供编程电位的电路和方法
公开(公告)号：US07538598B1
公开(公告)日：2009-05-26
申请号：US12172675
申请日：2008-07-14
申请人： John McCollum
发明人： John McCollum
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： A circuit for programming an antifuse coupled between a first node and a second node includes at least one transistor for supplying a programming potential VPP to the first node. A first transistor has a source coupled to a third node switchably coupleable between a potential of VPP/2 and ground potential, a drain, and a gate. A second transistor has a source coupled to the drain of the first transistor, a drain coupled to the second node, and a gate. Programming circuitry is coupled to the gate of the first transistor and the gate of the second transistor and configured to in a programming mode apply a potential of either zero volts or VPP/2 to the gate of the first transistor and to apply a potential of VPP/2 to the gate of the second transistor. The first and second transistors have a BVDss rating of not more than about VPP/2.
摘要翻译：用于编程耦合在第一节点和第二节点之间的反熔丝的电路包括用于向第一节点提供编程电位VPP的至少一个晶体管。第一晶体管具有耦合到可在VPP / 2的电位和地电位之间切换耦合的第三节点的源极，漏极和栅极。第二晶体管具有耦合到第一晶体管的漏极的源极，耦合到第二节点的漏极和栅极。编程电路耦合到第一晶体管的栅极和第二晶体管的栅极，并被配置为在编程模式中将零电压或VPP / 2的电位施加到第一晶体管的栅极并施加VPP的电位 / 2连接到第二晶体管的栅极。第一和第二晶体管具有不大于约VPP / 2的BVDss等级。

8. 发明授权

US07459763B1 Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material 有权
公开(公告)号：US07459763B1
公开(公告)日：2008-12-02
申请号：US10784903
申请日：2004-02-20
申请人： A. Farid Issaq , Frank Hawley , John McCollum
发明人： A. Farid Issaq , Frank Hawley , John McCollum
IPC分类号： H01L29/00 , H01L31/0312
CPC分类号： H01L23/5252 , G11C17/16 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.

9. 发明授权

US07443198B1 Non-volatile look-up table for an FPGA 失效
标题翻译： FPGA的非易失性查找表
公开(公告)号：US07443198B1
公开(公告)日：2008-10-28
申请号：US11929287
申请日：2007-10-30
申请人： John McCollum , Gregory Bakker , Jonathan Greene
发明人： John McCollum , Gregory Bakker , Jonathan Greene
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/1778 , H03K19/17728
摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A one input non-volatile-memory-transistor based lookup table is coupled to each of the n data inputs of the multiplexer. The multiplexer has X inputs wherein n=2X as is known in the art. A sense amplifier is coupled to the output of the multiplexer.
摘要翻译：用于FPGA的基于非易失性存储器晶体管的查找表包括n：1多路复用器。一个输入非易失性存储器 - 晶体管的查找表被耦合到多路复用器的每个n个数据输入端。多路复用器具有如本领域已知的具有n = 2×X的X个输入。读出放大器耦合到多路复用器的输出端。

10. 发明授权

US07430137B2 Non-volatile memory cells in a field programmable gate array 失效
标题翻译：现场可编程门阵列中的非易失性存储单元
公开(公告)号：US07430137B2
公开(公告)日：2008-09-30
申请号：US11868694
申请日：2007-10-08
申请人： Jonathan W. Greene , Fethi Dhaoui , Robert M. Salter, III , John McCollum
发明人： Jonathan W. Greene , Fethi Dhaoui , Robert M. Salter, III , John McCollum
IPC分类号： G11C16/02 , G11C5/02 , G11C5/06 , G06F7/38 , H03K19/173 , H03K19/177 , H03K19/94
CPC分类号： H03K19/1776 , G11C16/0441 , H03K19/17736 , H03K19/1778
摘要： A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor has a source, a drain, and a gate, the drain of the first p-channel MOS transistor electrically coupled to the drain of the first floating gate transistor forming a first common node. A second p-channel MOS transistor has a source, a drain, and a gate, the first drain of the second p-channel MOS transistor electrically coupled to the drain of the second floating gate transistor forming a second common node, the gate of the second p-channel MOS transistor electrically coupled to the first common node, and the second common node electrically coupled to the gate of the first p-channel MOS transistor.
摘要翻译：非易失性存储单元包括具有电耦合到行线的源极，漏极和栅极的第一浮栅晶体管。第二浮栅晶体管具有电耦合到行线的源极，漏极和栅极。第一p沟道MOS晶体管具有源极，漏极和栅极，第一p沟道MOS晶体管的漏极电耦合到第一浮动栅极晶体管的漏极，形成第一公共节点。第二p沟道MOS晶体管具有源极，漏极和栅极，第二p沟道MOS晶体管的第一漏极电耦合到形成第二公共节点的第二浮栅晶体管的漏极，栅极电耦合到第一公共节点的第二P沟道MOS晶体管，以及电耦合到第一p沟道MOS晶体管的栅极的第二公共节点。

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