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1. 发明申请

US20160321000A1 BIASING SCHEMES FOR STORAGE OF BITS IN UNRELIABLE STORAGE LOCATIONS 有权
标题翻译：在不可靠的存储位置存放位置的偏好方案
公开(公告)号：US20160321000A1
公开(公告)日：2016-11-03
申请号：US14700950
申请日：2015-04-30
申请人： SanDisk Technologies Inc.
发明人： Daniel Tuers , Abhijeet Manohar , Jonathan Hsu
IPC分类号： G06F3/06 , G06F12/14 , G11C16/06
CPC分类号： G06F3/0629 , G06F3/0619 , G06F3/0623 , G06F3/0679 , G06F11/1004 , G06F11/1012 , G06F12/1408 , G06F2212/402 , G11C16/10 , G11C16/3418 , G11C29/42 , G11C29/44 , G11C29/52 , G11C29/70 , G11C29/82 , G11C2029/0409
摘要： A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.
摘要翻译：非易失性存储器系统的控制器可以被配置为识别要存储在被识别为不可靠的非易失性存储器的存储器元件中的数据位。控制器可以被配置为将这些位中的至少一些偏置到预定的逻辑值，在该预定逻辑值处可能从不可靠的存储器元件读取位。控制器可以使用控制器基于位的识别产生的偏置键来进行。随后，当读取数据时，控制器可以分配比特的对数似然比值，以对应于被偏置到预定逻辑值的比特百分比似然性。这些位也可以使用偏置键无偏差。

2. 发明授权

US09589645B2 Block refresh to adapt to new die trim settings 有权
标题翻译：块刷新以适应新的模具修剪设置
公开(公告)号：US09589645B2
公开(公告)日：2017-03-07
申请号：US14507245
申请日：2014-10-06
申请人： SanDisk Technologies Inc.
发明人： Gautam Dusija , Chris Avila , Jonathan Hsu , Neil Darragh , Bo Lei
IPC分类号： G11C16/10 , G11C16/34 , G11C29/02 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459 , G11C29/028
摘要： Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time. A cell of a semiconductor memory may have a first charge level and be programmed with a first trim set. The cell may be reprogrammed by raising the first charge level to a second charge level that corresponds to the cell programmed with a second trim set.
摘要翻译：可以提供适应调整组提前的系统，装置和方法。修剪设置的进步可能会随着时间的推移而发生变化。半导体存储器的单元可以具有第一充电水平并且被编程为具有第一调整组。可以通过将第一充电电平升高到对应于用第二调整组编程的单元的第二充电水平来重新编程单元。

3. 发明申请

US20160225461A1 Memory System and Method for Reducing Read Disturb Errors 有权
标题翻译：用于减少读取干扰的存储器系统和方法
公开(公告)号：US20160225461A1
公开(公告)日：2016-08-04
申请号：US14675107
申请日：2015-03-31
申请人： SanDisk Technologies Inc.
发明人： Daniel E. Tuers , Abhijeet Manohar , Nicholas Thomas , Jonathan Hsu
IPC分类号： G11C16/34 , G11C11/56 , G11C16/26 , G11C14/00
CPC分类号： G11C16/3427 , G11C11/5642 , G11C16/26 , G11C16/3431
摘要： A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of memory and a controller. The controller is configured to detect a read disturb error in a block, identify data that caused the read disturb error, and move the data that caused the read disturb error to a block with a higher read endurance. This can be done by assigning read counters to blocks to determine frequently-read data, and storing that data in a separate block until it is less frequently read and will likely not cause additional read disturb errors.
摘要翻译：公开了一种用于减少读扰扰误差的存储系统和方法。在一个实施例中，提供了包括多个存储器块和控制器的存储器系统。控制器被配置为检测块中的读取干扰错误，识别导致读取干扰错误的数据，并将引起读取干扰错误的数据移动到具有较高读取耐久性的块。这可以通过将读计数器分配给块来确定频繁读取的数据，并将该数据存储在单独的块中，直到其被更少地读取并且可能不会引起额外的读取干扰错误。

4. 发明申请

US20160099057A1 BLOCK REFRESH TO ADAPT TO NEW DIE TRIM SETTINGS 有权
标题翻译：块改装适用于新的DIE TRIM设置
公开(公告)号：US20160099057A1
公开(公告)日：2016-04-07
申请号：US14507245
申请日：2014-10-06
申请人： SanDisk Technologies Inc.
发明人： Gautam Dusija , Chris Avila , Jonathan Hsu , Neil Darragh , Bo Lei
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459 , G11C29/028
摘要： Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time. A cell of a semiconductor memory may have a first charge level and be programmed with a first trim set. The cell may be reprogrammed by raising the first charge level to a second charge level that corresponds to the cell programmed with a second trim set.
摘要翻译：可以提供适应调整组提前的系统，装置和方法。修剪设置的进步可能会随着时间的推移而发生变化。半导体存储器的单元可以具有第一充电水平并且被编程为具有第一调整组。可以通过将第一充电电平升高到对应于用第二调整组编程的单元的第二充电水平来重新编程单元。

5. 发明授权

US09626106B2 System and method for memory command queue management and configurable memory status checking 有权
公开(公告)号：US09626106B2
公开(公告)日：2017-04-18
申请号：US14595878
申请日：2015-01-13
申请人： SanDisk Technologies Inc.
发明人： Jonathan Hsu , Daniel Tuers , Tien-chien Kuo
IPC分类号： G06F11/00 , G06F3/06 , G06F11/07
CPC分类号： G06F3/0604 , G06F3/061 , G06F3/0629 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F11/073 , G06F11/0751 , G06F11/079
摘要： Systems, apparatuses, and methods for command queue management and configurable memory status in a memory. A memory may include a controller and one or more memory integrated circuit chips, which each include memory arrays. The controller may send commands, such as read or write commands, to the one or more memory integrated circuit chips. The memory integrated circuit chips may maintain a command queue of the commands sent from the controller, thereby relieving the controller from such responsibility. Further, the memory integrated circuit chips may send an indication of an error in executing the commands, thereby relieving the controller from constant polling of the memory integrated circuit chips as to status.

6. 发明申请

US20160202914A1 SYSTEM AND METHOD FOR MEMORY COMMAND QUEUE MANAGEMENT AND CONFIGURABLE MEMORY STATUS CHECKING 有权
标题翻译：用于内存命令管理和可配置内存状态检查的系统和方法
公开(公告)号：US20160202914A1
公开(公告)日：2016-07-14
申请号：US14595878
申请日：2015-01-13
申请人： SanDisk Technologies Inc.
发明人： Jonathan Hsu , Daniel Tuers , Tien-chien Kuo
IPC分类号： G06F3/06 , G06F11/07
CPC分类号： G06F3/0604 , G06F3/061 , G06F3/0629 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F11/073 , G06F11/0751 , G06F11/079
摘要： Systems, apparatuses, and methods for command queue management and configurable memory status in a memory. A memory may include a controller and one or more memory integrated circuit chips, which each include memory arrays. The controller may send commands, such as read or write commands, to the one or more memory integrated circuit chips. The memory integrated circuit chips may maintain a command queue of the commands sent from the controller, thereby relieving the controller from such responsibility. Further, the memory integrated circuit chips may send an indication of an error in executing the commands, thereby relieving the controller from constant polling of the memory integrated circuit chips as to status.
摘要翻译：用于命令队列管理和内存中可配置内存状态的系统，设备和方法。存储器可以包括控制器和一个或多个存储器集成电路芯片，每个存储器集成电路芯片都包括存储器阵列。控制器可以向一个或多个存储器集成电路芯片发送诸如读取或写入命令的命令。存储器集成电路芯片可以维护从控制器发送的命令的命令队列，从而缓解控制器的这种责任。此外，存储器集成电路芯片可以在执行命令时发送错误的指示，从而缓解控制器对存储器集成电路芯片的状态的不断轮询。

7. 发明申请

US20150186259A1 METHOD AND APPARATUS FOR STORING DATA IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中存储数据的方法和装置
公开(公告)号：US20150186259A1
公开(公告)日：2015-07-02
申请号：US14144061
申请日：2013-12-30
申请人： SanDisk Technologies Inc.
发明人： Nicholas James Thomas , Jonathan Hsu , Igor Genshaft
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： Apparatus and methods implemented therein are disclosed for storing data in flash memories. The apparatus comprises a flash memory having several physical blocks, a logical to virtual mapping table, a virtual to physical mapping table and a memory controller. The memory controller retrieves a virtual block address from the logical to virtual mapping table. The virtual block address corresponds to an entry in the virtual to physical mapping table. The entry in the virtual to physical mapping table contains a reference to a physical block. The memory controller uses the virtual block address to retrieve the reference to the physical block and stores data in the physical block. The memory controller copies the stored data from the physical block to a second physical block. The memory controller then replaces the reference to the physical block contained in the entry of the virtual to physical mapping table with a reference to the second physical block.
摘要翻译：公开了其中实现的装置和方法，用于将数据存储在闪速存储器中。该装置包括具有多个物理块的闪速存储器，逻辑到虚拟映射表，虚拟到物理映射表和存储器控制器。内存控制器从逻辑到虚拟映射表检索虚拟块地址。虚拟块地址对应于虚拟物理映射表中的条目。虚拟物理映射表中的条目包含对物理块的引用。存储器控制器使用虚拟块地址来检索对物理块的引用并将数据存储在物理块中。存储器控制器将存储的数据从物理块复制到第二物理块。存储器控制器然后用对第二物理块的引用替代对虚拟物理映射表条目中包含的物理块的引用。

8. 发明授权

US10014060B2 Memory system and method for reducing read disturb errors 有权
公开(公告)号：US10014060B2
公开(公告)日：2018-07-03
申请号：US14675107
申请日：2015-03-31
申请人： SanDisk Technologies Inc.
发明人： Daniel E. Tuers , Abhijeet Manohar , Nicholas Thomas , Jonathan Hsu
IPC分类号： G11C16/34 , G11C11/56 , G11C16/26
CPC分类号： G11C16/3427 , G11C11/5642 , G11C16/26 , G11C16/3431
摘要： A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of memory and a controller. The controller is configured to detect a read disturb error in a block, identify data that caused the read disturb error, and move the data that caused the read disturb error to a block with a higher read endurance. This can be done by assigning read counters to blocks to determine frequently-read data, and storing that data in a separate block until it is less frequently read and will likely not cause additional read disturb errors.

9. 发明授权

US09830108B2 Write redirect 有权
公开(公告)号：US09830108B2
公开(公告)日：2017-11-28
申请号：US14880793
申请日：2015-10-12
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jonathan Hsu , Gautam Ashok Dusija , Tienchien Kuo , Daniel Edward Tuers
IPC分类号： G06F3/06
CPC分类号： G06F3/065 , G06F3/061 , G06F3/0616 , G06F3/0679
摘要： A data storage device includes a memory (including a single level cell (SLC) memory portion and a multilevel cell (MLC) memory portion), a plurality of data latches, and routing circuitry coupled to the plurality of data latches. The routing circuitry is configured to cause write data, received from a controller, to be stored at a data latch of the plurality of data latches. The routing circuitry is further configured to cause the write data to be copied from the data latch to a particular portion of the memory based on receiving a program mode command after the write data is stored at the data latch, where the program mode command indicates the particular portion as one of the SLC memory portion or the MLC memory portion.

10. 发明授权

US09720612B2 Biasing schemes for storage of bits in unreliable storage locations 有权
公开(公告)号：US09720612B2
公开(公告)日：2017-08-01
申请号：US14700950
申请日：2015-04-30
申请人： SanDisk Technologies Inc.
发明人： Daniel Tuers , Abhijeet Manohar , Jonathan Hsu
IPC分类号： G06F12/00 , G06F3/06 , G06F12/14 , G06F11/10 , G11C29/00 , G11C16/34 , G11C29/42 , G11C29/44 , G11C29/52 , G11C16/10 , G11C29/04
CPC分类号： G06F3/0629 , G06F3/0619 , G06F3/0623 , G06F3/0679 , G06F11/1004 , G06F11/1012 , G06F12/1408 , G06F2212/402 , G11C16/10 , G11C16/3418 , G11C29/42 , G11C29/44 , G11C29/52 , G11C29/70 , G11C29/82 , G11C2029/0409
摘要： A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

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