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1. 发明授权

US08988947B2 Back bias during program verify of non-volatile storage 有权
标题翻译：在非易失性存储的程序验证期间的背偏
公开(公告)号：US08988947B2
公开(公告)日：2015-03-24
申请号：US14213400
申请日：2014-03-14
申请人： SanDisk Technologies Inc.
发明人： Fumitoshi Ito
IPC分类号： G11C11/4197 , G11C16/34 , G11C16/04 , G11C16/10 , G11C11/56
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10
摘要： Different back bias (or body bias) conditions are applied to a non-volatile storage system during different program verify operations of a programming operation. A back bias may be applied during verify of an intermediate state (e.g., a lower page, middle page). The intermediate state is a state that exists during a program operation, but is not one of the final states. A lower back bias or no back bias is applied during verify of a final state (e.g., an upper page). Thus, a different back bias may be used when verifying an intermediate state than the back bias used when verifying a final state. Using the back bias makes it easier to verify a low VTH, such as a negative VTH. Also, using the back bias is effective at dealing with sense amplifier headroom issues.
摘要翻译：在编程操作的不同程序验证操作期间，将不同的背偏置（或体偏置）条件应用于非易失性存储系统。在验证中间状态（例如，下页，中间页）期间可以应用背偏置。中间状态是在程序操作期间存在但不是最终状态之一的状态。在验证最终状态（例如，上页）期间施加下背偏置或无背偏置。因此，当验证中间状态时，可以使用不同的背偏置，而不是在验证最终状态时使用的背偏压。使用反向偏置使得更容易验证低VTH，例如负VTH。此外，使用背偏置在处理读出放大器余量问题方面是有效的。

2. 发明申请

US20140269083A1 BIT LINE CURRENT TRIP POINT MODULATION FOR READING NONVOLATILE STORAGE ELEMENTS 有权
公开(公告)号：US20140269083A1
公开(公告)日：2014-09-18
申请号：US14290891
申请日：2014-05-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Man L. Mui , Teruhiko Kamei , Yingda Dong , Ken Oowada , Yosuke Kato , Fumitoshi Ito , Seungpil Lee
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.

3. 发明授权

US08942047B2 Bit line current trip point modulation for reading nonvolatile storage elements 有权
标题翻译：用于读取非易失性存储元件的位线电流跳变点调制
公开(公告)号：US08942047B2
公开(公告)日：2015-01-27
申请号：US14290891
申请日：2014-05-29
申请人： Sandisk Technologies Inc.
发明人： Man L. Mui , Teruhiko Kamei , Yingda Dong , Ken Oowada , Yosuke Kato , Fumitoshi Ito , Seungpil Lee
IPC分类号： G11C16/06 , G11C16/28 , G11C11/56 , G11C16/26
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.
摘要翻译：在选择要被感测的非易失性存储元件时，系统获得关于这些非易失性存储元件的位置的信息，至少部分地基于该信息来确定感测参数，对电荷存储装置进行预充电，并且在保持这些存储单元的位线的电压电平处于恒定值，将参考信号施加到这些非易失性存储元件一定的持续时间，然后确定在一定持续时间内由这些非易失性存储元件非易失存储元件超过预定值。

4. 发明申请

US20140286101A1 BACK BIAS DURING PROGRAM VERIFY OF NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储的程序验证期间返回偏差
公开(公告)号：US20140286101A1
公开(公告)日：2014-09-25
申请号：US14213400
申请日：2014-03-14
申请人： SanDisk Technologies Inc.
发明人： Fumitoshi Ito
IPC分类号： G11C16/34 , G11C16/04 , G11C16/10
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10
摘要： Different back bias (or body bias) conditions are applied to a non-volatile storage system during different program verify operations of a programming operation. A back bias may be applied during verify of an intermediate state (e.g., a lower page, middle page). The intermediate state is a state that exists during a program operation, but is not one of the final states. A lower back bias or no back bias is applied during verify of a final state (e.g., an upper page). Thus, a different back bias may be used when verifying an intermediate state than the back bias used when verifying a final state. Using the back bias makes it easier to verify a low VTH, such as a negative VTH. Also, using the back bias is effective at dealing with sense amplifier headroom issues.
摘要翻译：在编程操作的不同程序验证操作期间，将不同的背偏置（或体偏置）条件应用于非易失性存储系统。在验证中间状态（例如，下页，中间页）期间可以应用背偏置。中间状态是在程序操作期间存在但不是最终状态之一的状态。在验证最终状态（例如，上页）期间施加下背偏置或无背偏置。因此，当验证中间状态时，可以使用不同的背偏置，而不是在验证最终状态时使用的背偏压。使用反向偏置使得更容易验证低VTH，例如负VTH。此外，使用背偏置在处理读出放大器余量问题方面是有效的。

5. 发明申请

US20130097370A1 FABRICATING AND OPERATING A MEMORY ARRAY HAVING A MULTI-LEVEL CELL REGION AND A SINGLE-LEVEL CELL REGION 有权
标题翻译：制作和操作具有多层次细胞区域和单层细胞区域的记忆阵列
公开(公告)号：US20130097370A1
公开(公告)日：2013-04-18
申请号：US13706264
申请日：2012-12-05
申请人： SanDisk Technologies Inc.
发明人： Fumitoshi Ito , Shinji Sato
IPC分类号： G06F12/02
CPC分类号： G11C11/5621 , G11C2211/5641
摘要： Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times.
摘要翻译：本文公开了用于将不同的处理步骤应用于存储器阵列中的单级单元（SLC）块而不是多级单元（MLC）块的技术，使得SLC块将具有高耐久性并且MLC块将具有高可靠性。在一些方面，在MLC块中使用与SLC块不同的掺杂。在某些方面，在MLC块中使用与SLC块不同的隔离。公开了根据块被编程/擦除多少次来应用不同读取参数的技术。因此，使用与循环次数少的块不同的参数来读取已循环多次的块。

6. 发明授权

US08885416B2 Bit line current trip point modulation for reading nonvolatile storage elements 有权
标题翻译：用于读取非易失性存储元件的位线电流跳变点调制
公开(公告)号：US08885416B2
公开(公告)日：2014-11-11
申请号：US13754852
申请日：2013-01-30
申请人： Sandisk Technologies Inc.
发明人： Man L. Mui , Teruhiko Kamei , Yingda Dong , Ken Oowada , Yosuke Kato , Fumitoshi Ito , Seungpil Lee
IPC分类号： G11C16/06 , G11C16/28 , G11C11/56 , G11C16/26
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.
摘要翻译：在选择要被感测的非易失性存储元件时，系统获得关于这些非易失性存储元件的位置的信息，至少部分地基于该信息来确定感测参数，对电荷存储装置进行预充电，并且在保持这些存储单元的位线的电压电平处于恒定值，将参考信号施加到这些非易失性存储元件一定的持续时间，然后确定在一定持续时间内由这些非易失性存储元件非易失存储元件超过预定值。

7. 发明申请

US20140211568A1 BIT LINE CURRENT TRIP POINT MODULATION FOR READING NONVOLATILE STORAGE ELEMENTS 有权
标题翻译：用于读取非易失性存储元件的位线电流三点调制
公开(公告)号：US20140211568A1
公开(公告)日：2014-07-31
申请号：US13754852
申请日：2013-01-30
申请人： SANDISK TECHNOLOGIES INC.
发明人： Man L. Mui , Teruhiko Kamei , Yingda Dong , Ken Oowada , Yosuke Kato , Fumitoshi Ito , Seungpil Lee
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.
摘要翻译：在选择要被感测的非易失性存储元件时，系统获得关于这些非易失性存储元件的位置的信息，至少部分地基于该信息来确定感测参数，对电荷存储装置进行预充电，并且在保持这些存储单元的位线的电压电平处于恒定值，将参考信号施加到这些非易失性存储元件一定的持续时间，然后确定在一定持续时间内由这些非易失性存储元件非易失存储元件超过预定值。

8. 发明授权

US08503244B2 Fabricating and operating a memory array having a multi-level cell region and a single-level cell region 有权
标题翻译：制造和操作具有多级单元区域和单级单元区域的存储器阵列
公开(公告)号：US08503244B2
公开(公告)日：2013-08-06
申请号：US13706264
申请日：2012-12-05
申请人： SanDisk Technologies Inc.
发明人： Fumitoshi Ito , Shinji Sato
IPC分类号： G11C11/34
CPC分类号： G11C11/5621 , G11C2211/5641
摘要： Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times.
摘要翻译：本文公开了用于将不同的处理步骤应用于存储器阵列中的单级单元（SLC）块而不是多级单元（MLC）块的技术，使得SLC块将具有高耐久性并且MLC块将具有高可靠性。在一些方面，在MLC块中使用与SLC块不同的掺杂。在某些方面，在MLC块中使用与SLC块不同的隔离。公开了根据块被编程/擦除多少次来应用不同读取参数的技术。因此，使用与循环次数少的块不同的参数来读取已循环多次的块。

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