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1. 发明授权

US6081562A Implementing reduced-state viterbi detectors 失效
公开(公告)号：US6081562A
公开(公告)日：2000-06-27
申请号：US956309
申请日：1997-10-22
申请人： Runsheng He , Joao R. Cruz
发明人： Runsheng He , Joao R. Cruz
IPC分类号： H03M13/23 , H03M13/41 , H04L25/03 , H03D1/00 , H04L27/06
CPC分类号： H03M13/6343 , H03M13/41 , H03M13/4107 , H03M13/6502 , H04L25/03229
摘要： A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels are provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.

2. 发明授权

US06711213B2 Implementing reduced-state viterbi detectors 失效
标题翻译：实现降态维特比探测器
公开(公告)号：US06711213B2
公开(公告)日：2004-03-23
申请号：US10347889
申请日：2003-01-21
申请人： Runsheng He , Joao R. Cruz
发明人： Runsheng He , Joao R. Cruz
IPC分类号： H04L512
CPC分类号： H03M13/6343 , H03M13/41 , H03M13/4107 , H03M13/6502 , H04L25/03229
摘要： A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels are provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.
摘要翻译：提供了一种用于符号间干扰信道的简化状态维特比检测器的设计方法和实现系统。该方法使用补码状态分组技术，其包括找到补码状态之间的状态距离的步骤; 通过将状态距离不小于最小自由距离分组补码状态来形成缩小状态网格; 并保持状态距离小于最小自由距离不变的补码状态。所得到的降维态维特比检测器与全状态维特比检测器相比具有可忽略的性能损失，而复杂度降低了约两倍。

3. 发明授权

US06597742B1 Implementing reduced-state viterbi detectors 失效
标题翻译：实现降态维特比探测器
公开(公告)号：US06597742B1
公开(公告)日：2003-07-22
申请号：US09603703
申请日：2000-06-27
申请人： Runsheng He , Joao R. Cruz
发明人： Runsheng He , Joao R. Cruz
IPC分类号： H04L512
CPC分类号： H03M13/6343 , H03M13/41 , H03M13/4107 , H03M13/6502 , H04L25/03229
摘要： A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels are provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.
摘要翻译：提供了一种用于符号间干扰信道的简化状态维特比检测器的设计方法和实现系统。该方法使用补码状态分组技术，其包括找到补码状态之间的状态距离的步骤; 通过将状态距离不小于最小自由距离分组补码状态来形成缩小状态网格; 并保持状态距离小于最小自由距离不变的补码状态。所得到的降维态维特比检测器与全状态维特比检测器相比具有可忽略的性能损失，而复杂度降低了约两倍。

4. 发明授权

US08831552B1 RF band pass filter with feedback control 有权
标题翻译：具有反馈控制的RF带通滤波器
公开(公告)号：US08831552B1
公开(公告)日：2014-09-09
申请号：US11265074
申请日：2005-11-01
申请人： Runsheng He
发明人： Runsheng He
IPC分类号： H04B1/16
CPC分类号： H04B1/1638
摘要： A wireless receiver comprises a band-pass filter module that includes an input for receiving a first pilot signal, an output that generates a first signal based on the first pilot signal, and a control input for adjusting a center frequency of the band-pass filter module. A control module determines the energy of the first signal, generates a control signal based on the energy, and communicates the control signal to the control input of the band-pass filter module.
摘要翻译：无线接收机包括带通滤波器模块，其包括用于接收第一导频信号的输入，基于第一导频信号产生第一信号的输出，以及用于调整带通滤波器的中心频率的控制输入模块。控制模块确定第一信号的能量，基于能量产生控制信号，并将控制信号传送到带通滤波器模块的控制输入端。

5. 发明授权

US08711673B1 Mode detection for DVB receiver 失效
标题翻译： DVB接收机的模式检测
公开(公告)号：US08711673B1
公开(公告)日：2014-04-29
申请号：US13113399
申请日：2011-05-23
申请人： Jing Fang , Runsheng He , Zhipei Chi
发明人： Jing Fang , Runsheng He , Zhipei Chi
IPC分类号： H04J11/00
CPC分类号： H04L27/2666
摘要： Systems, apparatus and methods are provided for detecting the mode of a received OFDM signal. A received signal may be correlated with one or more time-delayed version of itself resulting in a set of correlation signals. Each correlation signal may be analyzed for one or more characteristics that can be used to determine the symbol length of the received signal. In order to minimize the number of correlations performed, one or more correlations can be used with varying symbol lengths and a fixed guard interval length. The correlation signals can be processed by filters, and the characteristics of the filtered correlation signals can be analyzed to determine the guard interval length of the received signal. In addition to detecting symbol length, the present invention can be used to detect receiver impairment and perform any appropriate compensations.
摘要翻译：提供了用于检测接收的OFDM信号的模式的系统，装置和方法。接收到的信号可以与自身的一个或多个时间延迟版本相关，从而产生一组相关信号。可以分析每个相关信号的一个或多个特性，其可用于确定接收信号的符号长度。为了最小化执行的相关数量，可以使用具有变化的符号长度和固定的保护间隔长度的一个或多个相关性。可以通过滤波器来处理相关信号，并且可以分析滤波的相关信号的特性以确定接收信号的保护间隔长度。除了检测符号长度之外，本发明可以用于检测接收机损伤并执行任何适当的补偿。

6. 发明授权

US08184802B1 Adaptive analog echo/next cancellation 有权
标题翻译：自适应模拟回波/下一个取消
公开(公告)号：US08184802B1
公开(公告)日：2012-05-22
申请号：US12215956
申请日：2008-07-01
申请人： Chen Xiaopeng , Runsheng He
发明人： Chen Xiaopeng , Runsheng He
IPC分类号： H04M9/08
CPC分类号： H04B3/32 , H04B3/23
摘要： An adaptive analog echo/near-end crosstalk (NEXT) cancellation system includes a bit slicer that receives a first analog receive signal and that generates a first error control signal. A digital signal processor (DSP) receives a digital receive signal and a digital transmit signal and generates second and third error control signals. A first summing module generates a fourth error control signal by summing the second and third error control signals. A selector outputs the first error control signal during a first mode and the fourth error control signal during a second mode. An echo/NEXT cancellation module communicates with the selector and generates an estimated echo/NEXT signal based on the first error control signal and an analog transmit signal during the first mode and based on the fourth error control signal and the analog transmit signal during the second mode.
摘要翻译：自适应模拟回波/近端串扰（NEXT）消除系统包括接收第一模拟接收信号并产生第一误差控制信号的位限幅器。数字信号处理器（DSP）接收数字接收信号和数字发射信号，并产生第二和第三误差控制信号。第一求和模块通过对第二和第三误差控制信号求和来产生第四误差控制信号。 A选择器在第一模式期间输出第一误差控制信号，在第二模式期间输出第四误差控制信号。回波/ NEXT消除模块与选择器通信，并且在第一模式期间基于第一误差控制信号和模拟发射信号，并且在第二模式期间基于第四误差控制信号和模拟发射信号，产生估计回波/ NEXT信号模式。

7. 发明授权

US08179144B1 Cable tester 有权
标题翻译：电缆测试仪
公开(公告)号：US08179144B1
公开(公告)日：2012-05-15
申请号：US13023410
申请日：2011-02-08
申请人： William Lo , Yiqing Guo , Tak Tsui , Tsin-Ho Leung , Runsheng He , Eric Janofsky
发明人： William Lo , Yiqing Guo , Tak Tsui , Tsin-Ho Leung , Runsheng He , Eric Janofsky
IPC分类号： G01R31/11
CPC分类号： H04L43/50 , G01R31/11 , H04L12/10
摘要： A network device including a physical layer (PHY) device and an autonegotiation module. The PHY device is configured to interface with N cable pairs, where N is greater than 1. The PHY device includes a cable test module configured to diagnose a short circuit in one of the N cable pairs. The autonegotiation module is configured to i) selectively perform autonegotiation to establish a link with a link partner at one of a first link speed and a second link speed that is lower than the first link speed, and ii) select between the first link speed and the second link speed in response to the cable test module diagnosing the short circuit.
摘要翻译：一种包括物理层（PHY）设备和自动协商模块的网络设备。 PHY设备被配置为与N个大于1的N个电缆对接口。PHY设备包括被配置为诊断N个电缆对之一中的短路的电缆测试模块。自动协商模块被配置为：i）选择性地执行自动协商以便以低于第一链路速度的第一链路速度和第二链路速度中的一个建立与链路伙伴的链路，以及ii）在第一链路速度和响应于电缆测试模块诊断短路的第二链路速度。

8. 发明授权

US08059773B1 Channel equalization in receivers 有权
标题翻译：接收机中的信道均衡
公开(公告)号：US08059773B1
公开(公告)日：2011-11-15
申请号：US12916167
申请日：2010-10-29
申请人： Runsheng He , Jing Fang
发明人： Runsheng He , Jing Fang
IPC分类号： H04B1/10
CPC分类号： H04L25/022 , H04L25/025 , H04L25/03159 , H04L25/03821
摘要： Apparatus and methods relating to channel equalization include a method including: generating a first output signal in a frequency domain based on a communications signal of a channel; determining a first channel response based on the first output signal and one or more pilot signals of the communications signal; generating a first equalized signal based on the first output signal and the first determined channel response; generating a first decision signal based on the first equalized signal; generating an output signal in a time domain based on the first decision signal; determining a second channel response based on the time domain output signal; generating a second output signal in the frequency domain based on the second channel response; generating a second equalized signal based on the first and second output signals and the time domain output signal; and generating a second decision signal based on the second equalized signal.
摘要翻译：与信道均衡相关的装置和方法包括：一种方法，包括：基于信道的通信信号产生频域中的第一输出信号; 基于所述第一输出信号和所述通信信号的一个或多个导频信号确定第一信道响应; 基于所述第一输出信号和所述第一确定的信道响应产生第一均衡信号; 基于所述第一均衡信号产生第一判定信号; 基于所述第一判定信号在时域中产生输出信号; 基于时域输出信号确定第二信道响应; 基于第二信道响应在频域中产生第二输出信号; 基于第一和第二输出信号和时域输出信号产生第二均衡信号; 以及基于所述第二均衡信号产生第二判定信号。

9. 发明授权

US07973524B1 Mixed mode digital control for switching regulator 有权
标题翻译：混合模式数字控制开关稳压器
公开(公告)号：US07973524B1
公开(公告)日：2011-07-05
申请号：US12858549
申请日：2010-08-18
申请人： Runsheng He
发明人： Runsheng He
IPC分类号： G05F1/40
CPC分类号： H02M3/1588 , H02M2001/0012 , Y02B70/1466
摘要： A regulated power supply includes an inverter comprising an upper switch and a lower switch that are connected in series. A control module selectively controls the upper switch and the lower switch in one of a pulse width modulation (PWM) mode and a discrete control mode (DCM), receives a feedback signal from an output of the regulated power supply, and switches between the PWM mode and the DCM based on the feedback signal.
摘要翻译：稳压电源包括串联连接的上部开关和下部开关的逆变器。控制模块以脉冲宽度调制（PWM）模式和离散控制模式（DCM）中的一种选择性地控制上部开关和下部开关，从稳压电源的输出接收反馈信号，并且在PWM 模式和DCM基于反馈信号。

10. 发明授权

US07906949B1 Adaptive control loop 有权
标题翻译：自适应控制回路
公开(公告)号：US07906949B1
公开(公告)日：2011-03-15
申请号：US12148078
申请日：2008-04-16
申请人： Sehat Sutardja , Runsheng He , Jiancheng Zhang
发明人： Sehat Sutardja , Runsheng He , Jiancheng Zhang
IPC分类号： G05F1/40 , H02M7/10
CPC分类号： H03K17/122 , H02M3/157 , H02M3/158 , H03K5/1565 , H03K17/167 , H03K17/6871
摘要： A duty cycle estimator comprises an error generator that compares an output of a switching regulator to a reference to generate an output error, wherein the switching regulator operates in accordance with a switching period. An accumulator determines an accumulated error of the output error over a time period of at least N times the switching period of the switching regulator, where N is an integer. An adjustment determiner adjusts a duty cycle for the switching regulator based on the accumulated error of the output error over the time period.
摘要翻译：占空比估计器包括误差发生器，其将开关稳压器的输出与参考值进行比较以产生输出误差，其中开关稳压器根据开关周期进行工作。累加器在开关调节器的开关周期的至少N倍的时间周期内确定输出误差的累积误差，其中N是整数。调整确定器根据在该时间段内的输出误差的累计误差来调节开关调节器的占空比。

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