会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Partial texture loads
    • 局部纹理负载
    • US07609272B1
    • 2009-10-27
    • US11010972
    • 2004-12-13
    • Emmett M. KilgariffRui M. Bastos
    • Emmett M. KilgariffRui M. Bastos
    • G06T1/00G06T11/40G09G5/00
    • G06T15/005G06T15/04G06T15/80G09G5/363G09G2360/06G09G2360/18
    • Circuits, methods, and apparatus that provide for partial texture load instructions. Instead of one instruction that may take several shader passes to complete, several instructions are issued, where each instruction is an instruction to retrieve a part or portion of a texture. While each instruction is performed, the other shader circuits can perform other instructions, thus increasing the utilization of the shader circuits when large textures are read from memory. Since several shader passes may be required to read a texture, if a particular instruction needs the texture, one exemplary embodiment reorders instructions such that other instructions are performed before the particular instruction that needs the texture.
    • 提供部分纹理加载指令的电路,方法和设备。 代替一个可能需要几个着色器遍的指令,就会发出几条指令,其中每条指令都是一条用于检索纹理的一部分或部分的指令。 当执行每条指令时,其他着色器电路可以执行其他指令,从而在从存储器读取大纹理时增加着色器电路的利用率。 由于读取纹理可能需要几个着色器遍,如果特定指令需要纹理,则一个示例性实施例重新排列指令,使得在需要纹理的特定指令之前执行其他指令。
    • 7. 发明授权
    • Shader pixel storage in a graphics memory
    • 图形存储器中的着色器像素存储
    • US06985151B1
    • 2006-01-10
    • US10752783
    • 2004-01-06
    • Rui M. BastosWalter E. Donovan
    • Rui M. BastosWalter E. Donovan
    • G06F15/76
    • G06T1/60
    • Circuits, apparatus, and methods that enable a shader to read and write data from and to a memory location during a single pass through a graphics pipeline. Some embodiments of the present invention provide an increase in the number of buffers available to a shader. These buffers may be read/write (input/output) or read only (input) buffers. Another provides pixel store and pixel load commands that may be used as instructions in a shader program or program portion, and may appear at positions other than the end of the shader program or program portion. Other embodiments provide a data path between a shader and a graphics memory, typically through a frame buffer interface. This data path simplifies the timing of the above store (write) and load (read) commands. Various embodiments may incorporate one or more of these features.
    • 电路,设备和方法,使得着色器能够在单次通过图形管线期间从存储器位置读取和写入数据。 本发明的一些实施例提供了可用于着色器的缓冲器数量的增加。 这些缓冲器可以是读/写(输入/输出)或只读(输入)缓冲器。 另一个提供可以用作着色器程序或程序部分中的指令的像素存储和像素负载命令,并且可以出现在除着色器程序或程序部分的结尾之外的位置。 其他实施例通常通过帧缓冲器接口提供着色器和图形存储器之间的数据路径。 该数据通道简化了上述存储(写入)和加载(读取)命令的定时。 各种实施例可以并入这些特征中的一个或多个。
    • 9. 发明授权
    • Temporal antialiasing in a multisampling graphics pipeline
    • 多采样图形管道中的时间抗锯齿
    • US09208605B1
    • 2015-12-08
    • US12237605
    • 2008-09-25
    • Cass W. EverittRui M. Bastos
    • Cass W. EverittRui M. Bastos
    • G06T15/50G09G5/00G06T11/20
    • G06T15/503G06T11/203G06T15/50
    • Multisampling techniques provide temporal as well as spatial antialiasing. Coverage for a primitive is determined at multiple sample locations for a pixel. In one embodiment, coverage is determined using boundary equations representing a boundary surface of the primitive in a three-dimensional space-time. A shading value for the primitive is computed for the pixel and stored for each coverage sample location of the pixel that is covered by the primitive. The sample locations are distributed in both space and time, and multiple sample locations share a single shading computation. The multisampling techniques are extendable to other dimensions that correspond to other image attributes.
    • 多采样技术提供时间和空间抗锯齿。 在像素的多个采样位置确定原始图像的覆盖。 在一个实施例中,使用表示三维时空中的原语的边界表面的边界方程来确定覆盖。 为像素计算基元的阴影值,并为由原始图元覆盖的像素的每个覆盖样本位置存储。 样本位置分布在空间和时间上,多个样本位置共享一个阴影计算。 多采样技术可扩展到对应于其他图像属性的其他维度。