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1. 发明授权

US4768161A Digital binary array multipliers using inverting full adders 失效
标题翻译：使用反转全加器的数字二进制数组乘法器
公开(公告)号：US4768161A
公开(公告)日：1988-08-30
申请号：US930176
申请日：1986-11-14
申请人： Roland A. Bechade , William K. Hoffman , Clarence R. Ogilvie
发明人： Roland A. Bechade , William K. Hoffman , Clarence R. Ogilvie
IPC分类号： G06F7/53 , G06F7/508 , G06F7/52
CPC分类号： G06F7/5312 , G06F2207/3876
摘要： Digital binary multipliers are provided which include first and second inverting full adders, each having first, second and third input terminals and first and second output terminals, the first output terminal of the first adder being connected to the first input terminal of the second adder with the first, second and third input terminals and the first and second output terminals of the second adder having a relationship with respect to the input and output terminals of the first adder such that corresponding input and output terminals have opposite signal polarities or complementary terminals, i.e., when one of these input or output terminals of the first adder has a true polarity signal, its corresponding input or output terminal of the second adder has a complemented polarity signal.
摘要翻译：提供了数字二进制乘法器，其包括第一和第二反相全加器，每个具有第一，第二和第三输入端以及第一和第二输出端，第一加法器的第一输出端连接到第二加法器的第一输入端，第二加法器的第一，第二和第三输入端和第一和第二输出端相对于第一加法器的输入和输出端具有关系，使得相应的输入和输出端具有相反的信号极性或互补端，即当第一加法器的这些输入或输出端之一具有真正的极性信号时，其对应的第二加法器的输入或输出端具有互补的极性信号。

2. 发明授权

US4912339A Pass gate multiplexer 失效
标题翻译：通门复用器
公开(公告)号：US4912339A
公开(公告)日：1990-03-27
申请号：US280071
申请日：1988-12-05
申请人： Roland A. Bechade , Clarence R. Ogilvie
发明人： Roland A. Bechade , Clarence R. Ogilvie
IPC分类号： H03K17/00 , H03K17/693
CPC分类号： H03K17/693
摘要： A circuit is provided, of the multiplexer type, which includes pass gates having first and second P-channel field effect transistors and first and second N-channel field effect transistors, a first data signal is applied to first current-carrying electrodes of the first P-channel and first N-channel transistors with a second data signal applied to first current-carrying electrodes of the second P-channel and second N-channel transistors, second current-carrying electrodes of the first and second P-channel transistors being connected together and second current-carrying electrodes of the first and second N-channel transistors being connected together and coupled to the second current-carrying electrodes of the first and second P-channel transistors. A true control pulse is applied to control electrodes of the first N-channel transistor and of the second P-channel transistor and a complemented control pulse, i.e., the complement of the true control pulse, is applied to control electrodes of the first P-channel transistors and of the second N-channel transistor. An output of the circuit is coupled to the second current-carrying electrodes of the transistors to selectively receive the first and second data signals.

3. 发明授权

US09264150B2 Reactive metal optical security device and methods of fabrication and use 有权
标题翻译：反应性金属光学安全装置及其制造和使用方法
公开(公告)号：US09264150B2
公开(公告)日：2016-02-16
申请号：US13432414
申请日：2012-03-28
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Charles S. Woodruff , Sebastian T. Ventrone
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Charles S. Woodruff , Sebastian T. Ventrone
IPC分类号： H04B10/85 , G02B26/08
CPC分类号： H04B10/85 , G02B26/0816
摘要： A reactive metal optical security device for implementation in an optical network and/or system to provide a mechanism for disrupting the optical network and/or system. The security device includes a mirror comprising a reactive metal stack and configured to reflect an optical signal and receive an electrical signal. The security device further includes a semiconductor chip configured to send the electrical signal to the mirror.
摘要翻译：一种用于在光网络和/或系统中实现以提供用于中断光网络和/或系统的机制的无功金属光学安全装置。安全装置包括反射镜，其包括无功金属堆叠并且被配置为反射光信号并接收电信号。安全装置还包括被配置为将电信号发送到反射镜的半导体芯片。

4. 发明授权

US09052724B2 Electro-rheological micro-channel anisotropic cooled integrated circuits and methods thereof 有权
标题翻译：电流变微通道各向异性冷却集成电路及其方法
公开(公告)号：US09052724B2
公开(公告)日：2015-06-09
申请号：US13568248
申请日：2012-08-07
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie
IPC分类号： H01L23/34 , G05D23/00 , G05D23/19 , H01L23/38 , H01L23/473 , H05K7/20 , G06F1/20
CPC分类号： G05D23/1919 , G06F1/206 , H01L23/38 , H01L23/473 , H01L2224/16225 , H01L2924/1305 , H01L2924/15174 , H01L2924/15311 , H05K7/20272 , H05K7/20281 , H05K7/20518 , H01L2924/00
摘要： An integrated circuit chip having micro-channels formed in multiple regions of the integrated circuit chip and a method of cooling the integrated circuit chip. The method includes for any region of the multiple regions, allowing a coolant to flow through micro-channels of the region only when a temperature of the region exceed a first specified temperature and blocking the coolant from flowing through the micro-channels of the region when a temperature of the region is below a second specified temperature.
摘要翻译：具有形成在集成电路芯片的多个区域中的微通道的集成电路芯片和冷却集成电路芯片的方法。该方法包括对于多个区域的任何区域，只有当该区域的温度超过第一规定温度并且阻止冷却剂流过该区域的微通道时，冷却剂才能流过该区域的微通道，该区域的温度低于第二规定温度。

5. 发明申请

US20140074422A1 ADAPTIVE POWER CONTROL USING TIMING CANONICALS 有权
标题翻译：使用时代标准的自适应功率控制
公开(公告)号：US20140074422A1
公开(公告)日：2014-03-13
申请号：US13614564
申请日：2012-09-13
申请人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
发明人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
IPC分类号： G06F17/50 , G06F19/00 , G01R31/317
CPC分类号： G01R31/31718 , G01R31/3008
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译：由相同的电路设计制造多个数字电路。功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。数字电路分为不同的电压箱，每个电压箱都有漏电极限。已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。非瞬时存储介质存储电压仓的边界作为速度分组测试数据。功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

6. 发明申请

US20130249596A1 INACTIVITY TRIGGERED SELF CLOCKING LOGIC FAMILY 有权
标题翻译：不活动触发自锁定逻辑系列
公开(公告)号：US20130249596A1
公开(公告)日：2013-09-26
申请号：US13426776
申请日：2012-03-22
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, JR. , Sebastian T. Ventrone , Charles S. Woodruff
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, JR. , Sebastian T. Ventrone , Charles S. Woodruff
IPC分类号： H03K19/00
CPC分类号： H03K19/0966 , H03K19/0013
摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.
摘要翻译：电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中只有在本地逻辑设备中已经满足设置时间之后）。这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

7. 发明申请

US20120083913A1 SEMICONDUCTOR LAYER FORMING METHOD AND STRUCTURE 有权
标题翻译：半导体层形成方法和结构
公开(公告)号：US20120083913A1
公开(公告)日：2012-04-05
申请号：US12897021
申请日：2010-10-04
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/72
摘要： A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location.
摘要翻译：一种形成和电气结构的方法。该方法包括确定第一半导体器件需要工程改变顺序（ECO）。确定实现ECO所需的附加结构层。选择用于将附加结构层插入第一半导体器件内的第一插入点位置。第一插入点位置与用于第二半导体器件的设计内的第二插入点位置相关联。根据第一ECO产生第二半导体器件。第二半导体器件包括第二结构。第二结构包括与第一半导体器件中的第一结构相同的结构。第二结构形成在第二半导体器件内的与包含第一结构的第一半导体器件中的位置相关联的位置。第二半导体器件包括位于第二插入点位置内的附加结构层。

8. 发明授权

US08055925B2 Structure and method to optimize computational efficiency in low-power environments 有权
标题翻译：在低功耗环境下优化计算效率的结构和方法
公开(公告)号：US08055925B2
公开(公告)日：2011-11-08
申请号：US11779432
申请日：2007-07-18
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith Williams , Charles S. Woodruff
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith Williams , Charles S. Woodruff
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203
摘要： A method and structure to optimize computational efficiency in a low-power environment. The method includes determining an optimal point for maximizing computational efficiency in a low-power environment, and selectively controlling operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The structure includes a plurality of processing units, a load manager controlling selective parallel operation of at least one processing unit of the plurality of processing units, and an unregulated power source.
摘要翻译：一种在低功耗环境下优化计算效率的方法和结构。该方法包括确定用于在低功率环境中最大化计算效率的最佳点，以及根据确定的最佳点选择性地控制多个处理单元中的至少一个处理单元的操作。该结构包括多个处理单元，控制多个处理单元中的至少一个处理单元的选择性并行操作的负载管理器和未调节的电源。

9. 发明申请

US20100231306A1 POWER MANAGEMENT ARCHITECTURE AND METHOD OF MODULATING OSCILLATOR FREQUENCY BASED ON VOLTAGE SUPPLY 有权
标题翻译：电源管理架构和基于电压供应调制振荡器频率的方法
公开(公告)号：US20100231306A1
公开(公告)日：2010-09-16
申请号：US12787167
申请日：2010-05-25
申请人： Kenneth J. GOODNOW , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
发明人： Kenneth J. GOODNOW , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： H03L7/00 , G06F17/50
CPC分类号： H03K3/0315
摘要： A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.
摘要翻译：一种基于电压源调制逻辑时钟振荡器频率的方法和系统。该系统包括具有逻辑操作的逻辑单元和用于产生自适应时钟以匹配逻辑运算的装置。该器件被配置为使用电源电压作为独立变量来优化电压变化的器件参数。本发明还涉及电路所在的设计结构。

10. 发明申请

US20090287905A1 PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS 有权
标题翻译：处理器管道结构逻辑状态保持系统和方法
公开(公告)号：US20090287905A1
公开(公告)日：2009-11-19
申请号：US12121292
申请日：2008-05-15
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/3867 , G06F1/32 , G06F1/3287 , G06F11/1407 , G06F11/1441 , Y02D10/171
摘要： A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.
摘要翻译：公开了一种用于保留处理器流水线架构的逻辑状态的解决方案。比较器位于处理器流水线架构的两个阶段之间。存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。提供了与早期输出值相同的参考逻辑。逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态电容器。提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

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