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1. 发明授权

US6009263A Emulating agent and method for reformatting computer instructions into a standard uniform format 失效
标题翻译：将计算机指令重新格式化为标准统一格式的仿真代理和方法
公开(公告)号：US6009263A
公开(公告)日：1999-12-28
申请号：US901471
申请日：1997-07-28
申请人： Roger A. Golliver , Gautam Bhagwandas Doshi , Jerome C. Huck , Alan Hersh Karp , Sivakumar Makineni , Mike Morrison , Glen Colon-Bonet
发明人： Roger A. Golliver , Gautam Bhagwandas Doshi , Jerome C. Huck , Alan Hersh Karp , Sivakumar Makineni , Mike Morrison , Glen Colon-Bonet
IPC分类号： G06F5/01 , G06F9/30 , G06F9/45
CPC分类号： G06F9/30112 , G06F5/012
摘要： An emulating agent and method is provided that receives numbers having si, exponents and significands of varying lengths and possibly configured in a variety of incompatible formats and to reformat the numbers into a standard uniform format for uniform arithmetic computations in processors operating with different architectures. In one embodiment, the emulating agent has a three-field superset register configured to receive the sign of a number in a first field, the exponent of a number in a second field and the significand of a number in a third field, regardless of the original format of the number, resulting in a number represented in a standard uniform format for computation. The embodiment also allows high level access to the fields to allow users to control the size of the numbers inserted into the fields.
摘要翻译：提供了一种仿真代理和方法，其接收具有不同长度的符号，指数和有效值的数字，并且可能以各种不兼容的格式配置，并且将数字重新格式化为用于使用不同架构的处理器中的统一算术计算的标准统一格式。在一个实施例中，仿真代理具有三场超集合寄存器，其被配置为接收第一字段中的数字的符号，第二字段中的数字的指数和第三字段中的数字的有效数，而不管原始格式的数字，导致以标准统一格式表示的数字进行计算。该实施例还允许对字段的高级访问以允许用户控制插入到字段中的数字的大小。

2. 发明授权

US06249798B1 Method, apparatus and computer system for directly transferring and translating data between an integer processing unit and a floating point processing unit 失效
标题翻译：用于在整数处理单元和浮点处理单元之间直接传送和转换数据的方法，装置和计算机系统
公开(公告)号：US06249798B1
公开(公告)日：2001-06-19
申请号：US08728646
申请日：1996-10-10
申请人： Roger A. Golliver , Michael James Morrison , Glenn Colon-Bonet , Guatam Bhawandas Doshi , Jerome C. Huck , Alan Hersh Karp , Sivakumar Makineni
发明人： Roger A. Golliver , Michael James Morrison , Glenn Colon-Bonet , Guatam Bhawandas Doshi , Jerome C. Huck , Alan Hersh Karp , Sivakumar Makineni
IPC分类号： G06F738
CPC分类号： H03M7/24
摘要： An apparatus, a processor, a computer system and a method may be used to directly transfer and translate data between a memory format in an integer processing unit and a floating point format in a floating point processing unit. Data is stored in integer registers of the integer processing unit in a memory format and is stored in floating point registers of the floating point processing unit in a floating point format. A direct data link is provided between the integer register file of the integer processing unit and the floating point register file of the floating point processing unit. The direct data link includes a logic circuit which translates data between the memory format and the floating point format.
摘要翻译：可以使用装置，处理器，计算机系统和方法在浮点处理单元中的整数处理单元中的存储器格式和浮点格式之间直接传送和转换数据。数据以存储格式存储在整数处理单元的整数寄存器中，并以浮点格式存储在浮点处理单元的浮点寄存器中。在整数处理单元的整数寄存器文件和浮点处理单元的浮点寄存器文件之间提供直接数据链接。直接数据链路包括在存储器格式和浮点格式之间转换数据的逻辑电路。

3. 发明授权

US5928356A Method and apparatus for selectively controlling groups of registers 失效
标题翻译：用于选择性地控制寄存器组的方法和装置
公开(公告)号：US5928356A
公开(公告)日：1999-07-27
申请号：US947541
申请日：1997-10-11
申请人： Roger A. Golliver , Jerome C. Huck , Dale C. Morris
发明人： Roger A. Golliver , Jerome C. Huck , Dale C. Morris
IPC分类号： G06F9/30 , G06F9/318 , G06F9/46 , G06F9/312
CPC分类号： G06F9/30123 , G06F9/30076 , G06F9/30101 , G06F9/3013 , G06F9/462
摘要： A method and apparatus for controlling groups of registers includes a pluity of registers of the same type logically separated into a plurality of groups and a plurality of indicators corresponding to the plurality of groups of registers, each of the plurality of indicators identifying whether a corresponding group of registers has been modified by a task currently being executed by the processor. A control logic is also included, coupled to the plurality of registers, to selectively control the plurality of registers by group based at least in part on the plurality of indicators.
摘要翻译：用于控制寄存器组的方法和装置包括：逻辑上分成多个组的相同类型的多个寄存器和对应于多组寄存器的多个指示符，多个指示符中的每一个指示符标识相应组的寄存器已由当前由处理器执行的任务修改。还包括耦合到多个寄存器的控制逻辑，以至少部分地基于多个指示符按组选择性地控制多个寄存器。

4. 发明授权

US06845501B2 Method and apparatus for enabling a compiler to reduce cache misses by performing pre-fetches in the event of context switch 有权
标题翻译：用于使编译器能够通过在上下文切换的情况下执行预取来减少高速缓存未命中的方法和装置
公开(公告)号：US06845501B2
公开(公告)日：2005-01-18
申请号：US09917535
申请日：2001-07-27
申请人： Carol L. Thompson , Michael L. Zi gler , Jerome C. Huck , Lawrence D. K. B. Dwyer
发明人： Carol L. Thompson , Michael L. Zi gler , Jerome C. Huck , Lawrence D. K. B. Dwyer
IPC分类号： G06F9/38 , G06F9/45
CPC分类号： G06F9/383
摘要： A method for reducing cache memory misses in a computer that performs context switches between at least a first context and a second context. A First logic identifies a first prefetch region in a first memory element and a second logic identifies critical memory references within the first prefetch region during compilation of a computer program. The critical memory references within the first prefetch region correspond to data in cache memory if a context switch occurs from a process or thread associated with the second context to a process or thread associated with the first context during program execution. Third logic prefetches data associated with the identified critical memory references and stores the prefetched data in cache memory prior to a process or thread associated with the first context being resumed when a switch from the second context to the first context occurs during program execution.
摘要翻译：一种用于减少在至少第一上下文和第二上下文之间进行上下文切换的计算机中的高速缓冲存储器缺失的方法。 A第一逻辑识别第一存储器元件中的第一预取区域，并且第二逻辑在汇编计算机程序期间识别第一预取区域内的关键存储器引用。如果在程序执行期间如果从与第二上下文相关联的进程或线程发生到与第一上下文相关联的进程或线程的上下文切换，则第一预取区域内的关键内存引用对应于高速缓冲存储器中的数据。第三逻辑预取与所识别的关键存储器引用相关联的数据，并且当在程序执行期间发生从第二上下文到第一上下文的切换时，在与第一上下文相关联的进程或线程之前，将预取数据存储在高速缓冲存储器中。

5. 发明授权

US06408380B1 Execution of an instruction to load two independently selected registers in a single cycle 有权
标题翻译：执行在一个周期内加载两个独立选择的寄存器的指令
公开(公告)号：US06408380B1
公开(公告)日：2002-06-18
申请号：US09316446
申请日：1999-05-21
申请人： Jerome C. Huck , Glenn T. Colon-Bonet , Alan H. Karp , David A. Fotland , Dean A. Mulla
发明人： Jerome C. Huck , Glenn T. Colon-Bonet , Alan H. Karp , David A. Fotland , Dean A. Mulla
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/30098 , G06F9/384
摘要： Method and apparatus for storing and executing an instruction to load two independent registers with two values is disclosed. In one embodiment, a computer-readable medium is encoded with an instruction including an opcode field specifying that the instruction is an instruction to load two independent registers with a first value and a second value, a source field specifying the first value and the second value, a first target register field specifying a first target register to load with the first value; a second target register field specifying a second target register to load with the second value. A system to execute the instruction is also disclosed.
摘要翻译：公开了用于存储和执行用于加载具有两个值的两个独立寄存器的指令的方法和装置。在一个实施例中，计算机可读介质用包括指定该指令是用于加载具有第一值和第二值的两个独立寄存器的指令的指令进行编码，指定第一值和第二值的源字段指定第一目标寄存器以第一值加载的第一目标寄存器字段; 指定第二目标寄存器的第二目标寄存器字段，以加载第二值。还公开了执行该指令的系统。

6. 发明授权

US5948095A Method and apparatus for prefetching data in a computer system 失效
公开(公告)号：US5948095A
公开(公告)日：1999-09-07
申请号：US1548
申请日：1997-12-31
申请人： Judge K. Arora , Jack D. Mills , Jerome C. Huck
发明人： Judge K. Arora , Jack D. Mills , Jerome C. Huck
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/383
摘要： A method and apparatus for prefetching data in a computer system that includes a processor. A prefetch instruction is executed and, in response, data is prefetched from a memory location. It is determined if a memory exception occurred during the prefetching of the data. If a memory exception occurred, the exception is handled if the prefetch instruction indicates to do so.

7. 发明授权

US5596733A System for exception recovery using a conditional substitution instruction which inserts a replacement result in the destination of the excepting instruction 失效
标题翻译：使用条件替换指令进行异常恢复的系统，该指令将替换结果插入到除外指令的目的地
公开(公告)号：US5596733A
公开(公告)日：1997-01-21
申请号：US361874
申请日：1994-12-22
申请人： William S. Worley, Jr. , Jerome C. Huck , Rajiv Gupta
发明人： William S. Worley, Jr. , Jerome C. Huck , Rajiv Gupta
IPC分类号： G06F7/38 , G06F7/00 , G06F7/483 , G06F9/38 , G06F11/07 , G06F9/302
CPC分类号： G06F9/30076 , G06F11/0721 , G06F11/0793 , G06F9/3861 , G06F9/3877
摘要： A conditional substitution instruction is provided in an instruction set of a computer system to correct exceptions occurring during run-time. The conditional substitution instruction can be executed concurrently in a pipelined computer system with a potentially excepting instruction, or simultaneously in a wide computer system. The conditional substitution instruction substitutes a default value for the result of the potentially excepting instruction if the potentially excepting instruction produces one or more specified exceptions.
摘要翻译：在计算机系统的指令集中提供条件替换指令，以纠正在运行期间发生的异常。条件替换指令可以在具有潜在的除外指令的流水线计算机系统中同时执行，也可以在宽计算机系统中同时执行。如果潜在的除外指令产生一个或多个指定的异常，条件替换指令将代替潜在的除外指令的结果的默认值。

8. 发明授权

US06212539B1 Methods and apparatus for handling and storing bi-endian words in a floating-point processor 有权
标题翻译：用于在浮点处理器中处理和存储双向字的方法和装置
公开(公告)号：US06212539B1
公开(公告)日：2001-04-03
申请号：US09169483
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi
IPC分类号： G06F700
CPC分类号： G06F7/768 , G06F7/483
摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译：计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。每个状态字段都包含标志和控制信息。不同的浮点运算可能与不同的状态字段相关联。浮点状态寄存器的子字段可以在操作期间动态更新。替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。浮点数据可以以大端或小端格式存储。

9. 发明授权

US6151669A Methods and apparatus for efficient control of floating-point status register 有权
标题翻译：浮点状态寄存器的有效控制方法和装置
公开(公告)号：US6151669A
公开(公告)日：2000-11-21
申请号：US169481
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
IPC分类号： G06F7/00 , G06F7/76 , G06F9/30 , G06F9/302 , G06F9/32 , G06F9/38 , G06F15/00
CPC分类号： G06F9/30014 , G06F9/30094 , G06F9/3842
摘要： A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译：计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。每个状态字段都包含标志和控制信息。不同的浮点运算可能与不同的状态字段相关联。浮点状态寄存器的子字段可以在操作期间动态更新。替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。浮点数据可以以大端或小端格式存储。

10. 发明授权

US06119218A Method and apparatus for prefetching data in a computer system 有权
标题翻译：用于在计算机系统中预取数据的方法和装置
公开(公告)号：US06119218A
公开(公告)日：2000-09-12
申请号：US349839
申请日：1999-07-08
申请人： Judge K. Arora , Jack D. Mills , Jerome C. Huck
发明人： Judge K. Arora , Jack D. Mills , Jerome C. Huck
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/383
摘要： A method and apparatus for prefetching data in a computer system that inces a processor. A prefetch instruction is executed and, in response, data is prefetched from a memory location. It is determined if a memory exception occurred during the prefetching of the data. If a memory exception occurred, the exception is handled if the prefetch instruction indicates to do so.
摘要翻译：一种用于在包括处理器的计算机系统中预取数据的方法和装置。执行预取指令，作为响应，从存储器位置预取数据。确定在数据预取期间是否发生内存异常。如果发生内存异常，则如果预取指令指示这样做，则会处理异常。

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