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1. 发明授权

US4897779A Method and apparatus for optimizing inter-processor instruction transfers 失效
标题翻译：用于优化处理器间指令传输的方法和装置
公开(公告)号：US4897779A
公开(公告)日：1990-01-30
申请号：US221987
申请日：1988-07-20
申请人： Robert Dickson , W. Hugh Durdan , George M. Uhler
发明人： Robert Dickson , W. Hugh Durdan , George M. Uhler
IPC分类号： G06F15/16 , G06F9/38 , G06F13/42 , G06F15/163 , G06F15/177 , G06F17/16
CPC分类号： G06F9/3881 , G06F13/4213
摘要： A protocol for transferring instructions between asynchronous processors in a computer system is provided. Each instruction transfer requires the transfer of an opcode and a variable number of operands. The transfer is accomplished via a bus which interconnects the processors. The opcode and operands are assembled in a buffer in the sending processor and then transferred to the receiving processor in reverse order, i.e., operands first and opcode last. The receiving processor does not acknowledge any of the transfers until it receives the opcode which is always sent last. Upon receipt of the opcode, the receiving processor knows the instruction transfer is complete and sends the acknowledge signal immediately thereafter.

2. 发明授权

US5579504A Multi-processor computer system having shared memory, private cache memories, and invalidate queues having valid bits and flush bits for serializing transactions 失效
标题翻译：具有共享存储器，专用高速缓存存储器和具有有效位和无效位的无效队列的多处理器计算机系统用于串行化事务
公开(公告)号：US5579504A
公开(公告)日：1996-11-26
申请号：US407784
申请日：1995-03-17
申请人： Michael A. Callander , G. Michael Uhler , W. Hugh Durdan
发明人： Michael A. Callander , G. Michael Uhler , W. Hugh Durdan
IPC分类号： G06F12/08 , G06F15/16 , G06F15/177 , G06F9/28 , G06F12/12
CPC分类号： G06F12/0808
摘要： Multi-processor systems are often implemented using a common system bus as the communication mechanism between CPU, memory, and I/O adapters. It is also common to include features on each CPU module, such as cache memory, that enhance the performance of the execution of instructions in the CPU. Many architectures require that the hardware employ a mechanism by which the data in the individual CPU cache memories is kept consistent with data in main memory and with data in other cache memories. One such method involves each CPU monitoring transactions on the system bus, and taking appropriate action when a transaction appears on the bus which would render data in the CPU's cache incoherent. If the CPU uses queues to hold records of incoming transaction information until it can service them, the bus interface must guarantee that the queued items are processed by the cache in the correct order. If this is not done, certain types of shared data protocols fail to operate correctly. The present invention describes a method by which hardware can guarantee the serialization of transactions requiring service by the CPU cache. The serialization method described guarantees that shared memory protocols operate correctly.
摘要翻译：多处理器系统通常使用公共系统总线作为CPU，内存和I / O适配器之间的通信机制来实现。在每个CPU模块（如高速缓存存储器）上都包含功能，这些功能可以增强CPU中指令执行的性能。许多架构要求硬件采用一种机制，通过该机制，各个CPU缓存存储器中的数据与主存储器中的数据和其他高速缓冲存储器中的数据保持一致。一种这样的方法涉及每个CPU监视系统总线上的事务，并且当事务出现在总线上时将采取适当的动作，这将使得CPU高速缓存中的数据不连贯。如果CPU使用队列来保存传入事务信息的记录，直到它可以服务它们为止，则总线接口必须保证排队的项目以正确的顺序被缓存处理。如果没有这样做，某些类型的共享数据协议无法正常运行。本发明描述了一种硬件可以保证由CPU高速缓存需要服务的事务的串行化的方法。所述的串行化方法保证共享存储器协议正常工作。

3. 发明授权

US5625802A Apparatus and method for adapting a computer system to different architectures 失效
标题翻译：将计算机系统适应于不同架构的装置和方法
公开(公告)号：US5625802A
公开(公告)日：1997-04-29
申请号：US353754
申请日：1994-12-12
申请人： Hoe T. Cho , Maw Z. Jau , W. Hugh Durdan
发明人： Hoe T. Cho , Maw Z. Jau , W. Hugh Durdan
IPC分类号： G06F13/40
CPC分类号： G06F13/409
摘要： In a computer system, a mother-board is used to physically connect processor, memory, and input/output modules. The mother-board includes an adaptable processor bus for connecting the processor and memory modules, and an input/output bus for connecting the input/output modules, the processor and input/output bus are decoupled for communicating. A processor module including a bridge is used to coupled the processor and input/output buses, and to adapt the processor bus to a particular processor architectures.
摘要翻译：在计算机系统中，主板用于物理连接处理器，存储器和输入/输出模块。主板包括用于连接处理器和存储器模块的适应性处理器总线，以及用于连接输入/输出模块的输入/输出总线，处理器和输入/输出总线被去耦以进行通信。包括桥接器的处理器模块用于耦合处理器和输入/输出总线，并使处理器总线适应特定的处理器架构。

4. 发明授权

US5058006A Method and apparatus for filtering invalidate requests 失效
标题翻译：用于过滤无效请求的方法和装置
公开(公告)号：US5058006A
公开(公告)日：1991-10-15
申请号：US212416
申请日：1988-06-27
申请人： W. Hugh Durdan , Rebecca L. Stamm , G. Michael Uhler
发明人： W. Hugh Durdan , Rebecca L. Stamm , G. Michael Uhler
IPC分类号： G06F12/08 , G06F15/16 , G06F15/177
CPC分类号： G06F12/0808
摘要： An apparatus which filters the number of invalidates to be propagated onto a private processor bus is provided. This is desirable so that the processor bus is not overloaded with invalidate requests. The present invention describes a method of filtering the number of invalidates to be propagated to each processor. A memory interface filters the invalidates by using a second private bus, the invalidate bus, which communicates with the cache controller. The cache controller can tell the memory interface whether data corresponding to the address on the invalidate bus is resident in the private cache memory of that processor. In this way, the memory interface only has to request the private processor bus when necessary, in order to perform the invalidate.

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