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1. 发明授权

US08230634B1 Two piece upper receiver for firearms 失效
标题翻译：两件火器上接收器
公开(公告)号：US08230634B1
公开(公告)日：2012-07-31
申请号：US13105893
申请日：2011-05-12
申请人： Robert Bruce Davies , Robert Lynch Hogan
发明人： Robert Bruce Davies , Robert Lynch Hogan
IPC分类号： F41A21/00 , F41A21/48
CPC分类号： F41A3/66 , F41C23/16 , F41G11/003
摘要： A two piece upper receiver for a firearm including a first piece having a front end, a rear end, a top, and a bottom, the first piece constructed to operatively carry a bolt carrier and bolt, and to have a barrel coupled to the front end. The bottom is constructed to have a lower receiver coupled thereto. The first piece includes a backbone extending along the top between the front end and the rear end, the back bone having upwardly directed indexing surfaces. A second piece overlies the backbone and includes mating surfaces engaging the indexing surfaces, aligning the second piece with the first piece. A receiving structure is opposite the mating surfaces for receiving accessory devices mounted thereon. Fasteners fixedly attach the second piece to the first piece to form a complete upper receiver.
摘要翻译：一种用于枪械的两件式上接收器，包括具有前端，后端，顶部和底部的第一件，第一件构造成可操作地承载螺栓承载件和螺栓，并且具有联接到前部的筒结束。底部构造成具有与其耦合的较低的接收器。第一件包括沿着前端和后端之间的顶部延伸的骨架，后骨具有向上指向的分度表面。第二件覆盖在骨架上并包括与分度表面接合的配合表面，使第二件与第一件对准。接收结构与配合表面相对，用于接收安装在其上的附件装置。紧固件将第二件固定在第一件上以形成一个完整的上部接收器。

2. 发明授权

US08530963B2 Power semiconductor device and method therefor 有权
公开(公告)号：US08530963B2
公开(公告)日：2013-09-10
申请号：US11387209
申请日：2006-03-23
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L21/2815 , H01L21/76224 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L2224/05554 , H01L2224/48091 , H01L2924/1305 , H01L2924/13091 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

3. 发明授权

US08022485B2 Transistor structure having reduced input capacitance 有权
标题翻译：具有降低的输入电容的晶体管结构
公开(公告)号：US08022485B2
公开(公告)日：2011-09-20
申请号：US12248816
申请日：2008-10-09
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H01L27/088
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/41766 , H01L29/42376 , H01L29/66727 , H01L29/7811
摘要： A semiconductor device having reduced input capacitance is disclosed. The semiconductor device includes a pedestal region having a gate overlying a sidewall of the pedestal region and gate interconnect overlying a major surface of the pedestal region. The pedestal region includes a conductive shield layer (260). The conductive shield layer (260) is isolated from the gate of the transistor by more than one dielectric layer (330, 340, and 350) to reduce input capacitance. The pedestal region includes an air gap region (1525) to further lower the dielectric constant of the pedestal region between the gate/gate interconnect and the conductive shield layer (260).
摘要翻译：公开了具有降低的输入电容的半导体器件。半导体器件包括具有覆盖基座区域的侧壁的栅极和覆盖基座区域的主表面的栅极互连的基座区域。基座区域包括导电屏蔽层（260）。导电屏蔽层（260）通过多于一个的介电层（330,340和350）与晶体管的栅极隔离以减小输入电容。基座区域包括气隙区域（1525），以进一步降低栅极/栅极互连和导电屏蔽层（260）之间的基座区域的介电常数。

4. 发明申请

US20100032750A1 Power Semiconductor Device And Method Therefor 有权
标题翻译：功率半导体器件及其方法
公开(公告)号：US20100032750A1
公开(公告)日：2010-02-11
申请号：US12580390
申请日：2009-10-16
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L27/0296 , H01L21/2815 , H01L21/32055 , H01L21/56 , H01L21/76224 , H01L21/768 , H01L21/76838 , H01L21/823412 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L21/823487 , H01L23/047 , H01L23/051 , H01L23/10 , H01L23/36 , H01L23/3675 , H01L23/4824 , H01L23/49844 , H01L23/552 , H01L23/66 , H01L24/06 , H01L24/83 , H01L25/50 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/66681 , H01L29/66712 , H01L29/66719 , H01L29/66727 , H01L29/7811 , H01L29/7817 , H01L2223/6644 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/48091 , H01L2224/83193 , H01L2224/83801 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/0106 , H01L2924/01061 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/16152 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.
摘要翻译：功率晶体管包括多个晶体管单元。每个晶体管单元具有耦合到覆盖第一主表面的第一电极互连区域的第一电极，耦合到覆盖第一主表面的控制电极互连区域的控制电极，以及耦合到覆盖第二主表面的第二电极互连区域的第二电极主要表面。每个晶体管单元在沟道区中具有近似恒定的掺杂浓度。电介质平台用作外延层的边缘终端以在其中保持基本上平面的等电位线。功率晶体管在以超过500兆赫的频率工作的射频应用中具有特别的用途，并耗散5瓦以上的功率。半导体管芯和封装被设计成使得功率晶体管能够在如此恶劣的条件下有效地工作。

5. 发明申请

US20080048215A1 ELECTRICAL STRESS PROTECTION APPARATUS AND METHOD OF MANUFACTURE 有权
标题翻译：电力应力保护装置及其制造方法
公开(公告)号：US20080048215A1
公开(公告)日：2008-02-28
申请号：US11467452
申请日：2006-08-25
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H01L29/80
CPC分类号： H01L27/0262
摘要： In various embodiments, circuits and semiconductor devices and structures and methods to manufacture these structures and devices are disclosed. In one embodiment, a bidirectional polarity, voltage transient protection device is disclosed. The voltage transient protection device may include a bipolar PNP transistor having a turn-on voltage of VBE1, a bipolar NPN transistor having a turn-on voltage of VBE2, and a field effect transistor (FET) having a threshold voltage of VTH, wherein a turn-on voltage VTO of the voltage transient protection device is approximately equal to the sum of VBE1, VBE2, and VTH, that is, VTO≅VBE1+VBE2+VTH. Other embodiments are described and claimed.
摘要翻译：在各种实施例中，公开了用于制造这些结构和装置的电路和半导体器件及其结构和方法。在一个实施例中，公开了双向极性电压瞬变保护装置。电压瞬变保护装置可以包括具有导通电压V BAT1的双极性PNP晶体管，具有导通电压V BE2的双极性NPN晶体管，以及具有阈值电压V TH TH的场效应晶体管（FET），其中电压瞬变保护装置的导通电压V IN TO TO近似等于 V BE1 ，V BE2和V TH TH，这就是V≅V BE1 < / SUB + + + + + + + + H + 描述和要求保护其他实施例。

6. 发明授权

US08697556B2 Transistor structure having a trench drain 有权
标题翻译：具有沟槽漏极的晶体管结构
公开(公告)号：US08697556B2
公开(公告)日：2014-04-15
申请号：US13535804
申请日：2012-06-28
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H01L29/04
CPC分类号： H01L29/0882 , H01L21/26586 , H01L29/0653 , H01L29/0661 , H01L29/0878 , H01L29/402 , H01L29/41766 , H01L29/42376 , H01L29/66727 , H01L29/7802 , H01L29/7811
摘要： A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.
摘要翻译：半导体器件形成为具有与器件的载流区相邻的沟槽。形成沟槽的深度大于装置的桶区域的深度。增加沟槽深度将较高场强的区域从桶区移动到沿着沟槽的区域。沿着沟槽的区域不具有接合点并且可以承受更高的场强。

7. 发明申请

US20130034952A1 TRANSISTOR STRUCTURE HAVING A TRENCH DRAIN 有权
标题翻译：具有TRENCH DRAIN的晶体管结构
公开(公告)号：US20130034952A1
公开(公告)日：2013-02-07
申请号：US13535804
申请日：2012-06-28
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H01L21/265
CPC分类号： H01L29/0882 , H01L21/26586 , H01L29/0653 , H01L29/0661 , H01L29/0878 , H01L29/402 , H01L29/41766 , H01L29/42376 , H01L29/66727 , H01L29/7802 , H01L29/7811
摘要： A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.
摘要翻译：半导体器件形成为具有与器件的载流区相邻的沟槽。形成沟槽的深度大于装置的桶区域的深度。增加沟槽深度将较高场强的区域从桶区移动到沿着沟槽的区域。沿着沟槽的区域不具有接合点并且可以承受更高的场强。

8. 发明授权

US07999250B2 Silicon-germanium-carbon semiconductor structure 有权
标题翻译：硅 - 锗 - 碳半导体结构
公开(公告)号：US07999250B2
公开(公告)日：2011-08-16
申请号：US12394285
申请日：2009-02-27
申请人： Bishnu Prasanna Gogoi , Robert Bruce Davies
发明人： Bishnu Prasanna Gogoi , Robert Bruce Davies
IPC分类号： H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L29/10 , H01L29/04 , H01L31/036 , H01L31/0376 , H01L31/20 , H01L29/12
CPC分类号： H01L29/7811 , H01L21/2815 , H01L29/0653 , H01L29/0661 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/161 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/42376 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/7802
摘要： In accordance with one or more embodiments, a semiconductor structure includes a semiconductor substrate, a first semiconductor material over the semiconductor substrate, and a second semiconductor material over a portion the first semiconductor material, wherein the second semiconductor material comprises silicon-germanium-carbon (SiGeC) and wherein the first semiconductor material is a silicon epitaxial layer. The semiconductor structure further includes an active device, wherein a portion of the active device is formed in the second semiconductor material and a dielectric structure extending from the first surface of the first semiconductor material into the semiconductor substrate through the first semiconductor material.
摘要翻译：根据一个或多个实施例，半导体结构包括半导体衬底，半导体衬底上的第一半导体材料和第一半导体材料部分上的第二半导体材料，其中第二半导体材料包括硅 - 锗 - 碳（ SiGeC），并且其中所述第一半导体材料是硅外延层。半导体结构还包括有源器件，其中有源器件的一部分形成在第二半导体材料中，以及电介质结构，通过第一半导体材料从第一半导体材料的第一表面延伸到半导体衬底中。

9. 发明申请

US20100090291A1 TRANSISTOR STRUCTURE HAVING REDUCED INPUT CAPACITANCE 有权
标题翻译：具有降低输入电容的晶体管结构
公开(公告)号：US20100090291A1
公开(公告)日：2010-04-15
申请号：US12248816
申请日：2008-10-09
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/41766 , H01L29/42376 , H01L29/66727 , H01L29/7811
摘要： A semiconductor device having reduced input capacitance is disclosed. The semiconductor device includes a pedestal region having a gate overlying a sidewall of the pedestal region and gate interconnect overlying a major surface of the pedestal region. The pedestal region includes a conductive shield layer (260). The conductive shield layer (260) is isolated from the gate of the transistor by more than one dielectric layer (330, 340, and 350) to reduce input capacitance. The pedestal region includes an air gap region (1525) to further lower the dielectric constant of the pedestal region between the gate/gate interconnect and the conductive shield layer (260).
摘要翻译：公开了具有降低的输入电容的半导体器件。半导体器件包括具有覆盖基座区域的侧壁的栅极和覆盖基座区域的主表面的栅极互连的基座区域。基座区域包括导电屏蔽层（260）。导电屏蔽层（260）通过多于一个的介电层（330,340和350）与晶体管的栅极隔离以减小输入电容。基座区域包括气隙区域（1525），以进一步降低栅极/栅极互连和导电屏蔽层（260）之间的基座区域的介电常数。

10. 发明授权

US4021701A Transistor protection circuit 失效
标题翻译：晶体管保护电路
公开(公告)号：US4021701A
公开(公告)日：1977-05-03
申请号：US638879
申请日：1975-12-08
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： G05F1/573 , H03F1/52 , H02H7/20
CPC分类号： H03F1/52 , G05F1/573
摘要： The disclosed protection circuit which is suitable for providing protection of transistors included in integrated circuits such as regulators and power amplifiers, includes thermal shutdown, safe area and current control circuits. The current control portion includes a sense transistor connected substantially in parallel with the transistor to be protected. In monolithic integrated circuit applications, the sense transistor has an emitter area that is a predetermined ratio of the emitter area of the protected transistor. A "sense resistor" is connected to the sense transistor and develops a control signal which is proportional to the instantaneous current being conducted by the protected transistor. A threshold circuit is coupled between the sense resistor and the drive circuit for the protected transistor and responds to the magnitude of the control signal crossing a predetermined threshold to remove or reduce the drive to the protected transistor.
摘要翻译：所公开的适用于提供包括在诸如调节器和功率放大器的集成电路中的晶体管的保护的保护电路包括热关断，安全区域和电流控制电路。电流控制部分包括基本上与要保护的晶体管并联连接的检测晶体管。在单片集成电路应用中，感测晶体管具有作为受保护晶体管的发射极面积的预定比率的发射极区域。 “感测电阻器”连接到感测晶体管，并产生与受保护晶体管传导的瞬时电流成正比的控制信号。阈值电路耦合在感测电阻器和用于受保护晶体管的驱动电路之间，并且响应于超过预定阈值的控制信号的大小以去除或减小对受保护晶体管的驱动。

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