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1. 发明授权

US5701495A Scalable system interrupt structure for a multi-processing system 失效
标题翻译：多处理系统的可扩展系统中断结构
公开(公告)号：US5701495A
公开(公告)日：1997-12-23
申请号：US573918
申请日：1995-12-18
申请人： Richard Louis Arndt , James Otto Nicholson , Edward John Silha , Steven Mark Thurber , Amy May Youngs
发明人： Richard Louis Arndt , James Otto Nicholson , Edward John Silha , Steven Mark Thurber , Amy May Youngs
IPC分类号： G06F15/16 , G06F9/46 , G06F9/48 , G06F13/24 , G06F15/177
CPC分类号： G06F9/4812
摘要： An interrupt subsystem within a data processing system is scalable from low-end uni-processor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queueing of interrupts from many sources, and for queueing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.
摘要翻译：数据处理系统中的中断子系统可从低端单处理器系统扩展到高端多处理器（MP）系统。该中断子系统提供了来自多个源的中断排队，以及用于将中断排队到多处理器系统中的最佳处理器。外部中断机制分为两层，一个中断路由层和一个中断表示层。中断路由层将中断条件路由到中断表示层中的中断管理区域的适当实例。中断表示层将中断源传送到服务/处理中断的系统软件。通过在中断子系统内提供两层，可以写入独立于中断类型或来源的应用程序或系统软件。中断路由层从软件隐藏了特定硬件实现的细节。中断演示层与系统和/或应用软件接口，并提供独立于硬件的功能。

2. 发明授权

US5673399A System and method for enhancement of system bus to mezzanine bus transactions 失效
标题翻译：将系统总线增强到夹层总线交易的系统和方法
公开(公告)号：US5673399A
公开(公告)日：1997-09-30
申请号：US552034
申请日：1995-11-02
申请人： Guy Lynn Guthrie , Danny Marvin Neal , Edward John Silha , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Danny Marvin Neal , Edward John Silha , Steven Mark Thurber
IPC分类号： G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. The host bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information. The inbound path is a mirror image of the outbound path with read requests and write requests being stored in a sequential buffer and read replies being stored in a number of parallel buffers. Both the inbound path and the outbound path in the host bridge are controlled by a state machine which takes into consideration activity in both directions and permits or inhibits bypass transactions based on the protocol of the buses being interconnected through the bridge.
摘要翻译：数据处理系统包括主处理器，多个外围设备以及可以在主机，外围设备和其他主机或诸如网络中的外围设备之间连接的一个或多个网桥。每个桥梁（如PCI主机桥）连接在主总线（例如系统总线）和辅助总线之间，为了清楚起见，主总线将被视为出站事务的来源和入站事务的目的地，辅助总线将被视为出站交易的目的地和入站交易的来源。主桥包括出站数据路径，入站数据路径和控制机制。出站数据路径包括排队缓冲器，用于按照从主总线接收的顺序存储事务，其中排队缓冲器中的请求可以在读请求和写事务之间混合，出站路径还包括多个用于存储读取的并行缓冲器回复数据和地址信息。入站路径是出站路径的镜像，读取请求和写入请求存储在顺序缓冲区中，并且读取回复存储在多个并行缓冲区中。主桥中的入站路径和出站路径都由状态机控制，该状态机考虑到两个方向的活动，并且基于通过桥互连的总线的协议允许或禁止旁路交易。

3. 发明授权

US6134621A Variable slot configuration for multi-speed bus 失效
标题翻译：多速总线可变插槽配置
公开(公告)号：US6134621A
公开(公告)日：2000-10-17
申请号：US092153
申请日：1998-06-05
申请人： Richard Allen Kelley , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
IPC分类号： G06F13/14 , G06F13/40 , G06F13/00 , G06F1/08 , G06F13/38
CPC分类号： G06F13/4068
摘要： A method and apparatus are provided in which a control scheme is implemented to enable a PCI bus to operate more than two PCI slots into which PCI devices may be installed. The PCI slots are checked to determine if a PCI device is installed in the slots and the speed at which the installed PCI devices are capable of running. If any of the slots has a 33 MHz device installed in any of the slots, the system is enabled to run more than two slots, and all of the PCI devices will run at 33 MHz. When no 33 MHz cards or devices are installed in the PCI slots, and PCI devices are only installed in the first two slots, then the system is enabled to run only the first two slots at the speed of 66 MHz. In one alternative embodiment, a default configuration routine sets the PCI bus speed at one of the operating frequencies and modifies that default if it is determined during a system configuration cycle that another speed is more appropriate.
摘要翻译：提供了一种方法和装置，其中实现控制方案以使得PCI总线能够操作可以安装PCI设备的两个以上PCI插槽。检查PCI插槽以确定PCI设备是否安装在插槽中以及安装的PCI设备能够运行的速度。如果任何插槽中的任何一个插槽中都安装了一个33 MHz器件，则系统可以运行多于两个插槽，所有PCI设备将以33 MHz运行。当PCI插槽中没有安装33 MHz的卡或设备时，PCI设备仅安装在前两个插槽中，则系统只能以66 MHz的速度运行前两个插槽。在一个替代实施例中，默认配置例程将PCI总线速度设置为工作频率之一，并且如果在系统配置周期期间确定另一个速度更合适，则修改该默认值。

4. 发明授权

US06223299B1 Enhanced error handling for I/O load/store operations to a PCI device via bad parity or zero byte enables 失效
标题翻译：通过坏的奇偶校验或零字节使I / O加载/存储操作到PCI设备的增强的错误处理能够实现
公开(公告)号：US06223299B1
公开(公告)日：2001-04-24
申请号：US09072418
申请日：1998-05-04
申请人： Douglas Craig Bossen , Charles Andrew McLaughlin , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
发明人： Douglas Craig Bossen , Charles Andrew McLaughlin , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
IPC分类号： G06F1100
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0793
摘要： Device selects lines from each I/O device are brought into a PCI host bridge individually so that the device number of a failing device may be logged in an error register when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity of zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear. Normal system operations are thus not impacted, and operations during error recovery are permitted to proceed if no further damage will be caused by such operations.
摘要翻译：设备选择每个I / O设备的线路分别插入PCI主机桥，以便在PCI总线上出现错误时，可能会将故障设备的设备号记录在错误寄存器中。在错误寄存器复位之前，后续的加载和存储操作将被延迟，直到可以针对错误寄存器检查主体设备的设备编号。如果主机设备是先前发生故障的设备，则通过强制坏的奇偶校验或归零所有字节使能来防止对该设备的加载/存储操作完成。通过强制零字节的不良奇偶使能，I / O设备将通过激活其设备选择行来响应加载或存储请求，但不接受存储数据。允许对未登录在错误寄存器中的设备进行操作，正常情况下，正常情况下进行加载存储操作。因此，正常的系统操作不会受到影响，并且如果这种操作不会造成进一步的损坏，则允许错误恢复期间的操作进行。

5. 发明授权

US08782024B2 Managing the sharing of logical resources among separate partitions of a logically partitioned computer system 失效
标题翻译：管理逻辑分区计算机系统的不同分区之间的逻辑资源共享
公开(公告)号：US08782024B2
公开(公告)日：2014-07-15
申请号：US10777724
申请日：2004-02-12
申请人： Richard Louis Arndt , Bruce G. Mealey , Steven Mark Thurber
发明人： Richard Louis Arndt , Bruce G. Mealey , Steven Mark Thurber
IPC分类号： G06F7/00
CPC分类号： G06F9/45533 , G06F9/45541 , G06F9/5077
摘要： A mechanism is provided for sharing resources among logical partitions in a logical partitioned data processing system and for managing the changes to resources in such a way that the sharing operating systems are able to handle the various transitions in a graceful manner. Four hypervisor functions plus a specific return code manage the granting of access of resources owned by one partition to another (client) partition, accepting of granted resources by client partitions, returning of granted resources by client partitions, and rescinding of access by the owning partition. These four hypervisor functions are invoked either explicitly by the owning and client partitions or automatically by the hypervisor in response to partition termination. The hypervisor functions provide the needed infrastructure to manage the sharing of logical resources among partitions.
摘要翻译：提供了一种用于在逻辑分区数据处理系统中的逻辑分区之间共享资源并且以这样的方式管理对资源的改变的机制，使得共享操作系统能够以优雅的方式处理各种转换。四个管理程序功能加上特定的返回代码管理一个分区所拥有的资源到另一个（客户端）分区的授权，客户端分区接受授予的资源，客户机分区返回授权资源，以及由所拥有的分区撤销访问。这四个虚拟机管理程序功能由拥有和客户机分区明确地调用，或者由管理程序自动地响应于分区终止而调用。管理程序功能提供所需的基础设施来管理分区之间逻辑资源的共享。

6. 发明授权

US08213294B2 Mechanism for detecting and clearing I/O fabric lockup conditions for error recovery 有权
标题翻译：用于检测和清除I / O结构锁定条件以进行错误恢复的机制
公开(公告)号：US08213294B2
公开(公告)日：2012-07-03
申请号：US11426592
申请日：2006-06-27
申请人： Richard Louis Arndt , Thomas Schlipf , Steven Mark Thurber
发明人： Richard Louis Arndt , Thomas Schlipf , Steven Mark Thurber
IPC分类号： G01R31/08
CPC分类号： H04L47/10 , H04L41/0659 , H04L47/11 , H04L47/30 , H04L47/32 , H04L47/39 , H04L49/90
摘要： A computer implemented method, apparatus and mechanism for recovery of an I/O fabric that has become terminally congested or deadlocked due to a failure which causes buffers/queues to fill and thereby causes the root complexes to lose access to their I/O subsystems. Upon detection of a terminally congested or deadlocked transmit queue, access to such queue by other root complexes is suspended while each item in the queue is examined and processed accordingly. Store requests and DMA read reply packets in the queue are discarded, and load requests in the queue are processed by returning a special completion package. Access to the queue by the root complexes is then resumed.
摘要翻译：用于恢复I / O结构的计算机实现的方法，装置和机制，其由于导致缓冲器/队列填充并由此导致根配置失去对其I / O子系统的访问的故障而变得终端拥塞或死锁。在检测到最终拥塞或死锁传输队列时，暂停其他根组合对这样的队列的访问，同时对队列中的每个项目进行相应的检查和处理。队列中存储请求和DMA读回应数据包将被丢弃，队列中的加载请求将通过返回特殊的完成包进行处理。然后恢复根组合对队列的访问。

7. 发明授权

US07734842B2 Computer-implemented method, apparatus, and computer program product for managing DMA write page faults using a pool of substitute pages 有权
标题翻译：计算机实现的方法，设备和计算机程序产品，用于使用替代页面池管理DMA写页错误
公开(公告)号：US07734842B2
公开(公告)日：2010-06-08
申请号：US11390790
申请日：2006-03-28
申请人： Richard Louis Arndt , Steven Mark Thurber
发明人： Richard Louis Arndt , Steven Mark Thurber
IPC分类号： G06F13/28 , G06F12/08
CPC分类号： G06F11/141 , G06F12/08 , G06F12/1081
摘要： A computer-implemented method, apparatus, and computer program product are disclosed for managing direct memory access (DMA) write page faults using a pool of substitute pages. A computer system platform resolves a DMA write page fault for a page that is dedicated to an Input/Output (I/O) adapter. The I/O adapter attempts to write DMA data to the page. A determination is made that the page is unavailable for writing. The DMA data is then written to data locations in a substitute page that was selected from the pool of substitute pages. A flag is then set in a flag location for each one of the data locations. The flag locations correspond to the data locations. When a flag is set, the flag indicates that DMA write data is present in the data location that corresponds to that flag's flag location.
摘要翻译：公开了一种计算机实现的方法，装置和计算机程序产品，用于使用替代页面池来管理直接存储器访问（DMA）写页错误。计算机系统平台解决专用于输入/输出（I / O）适配器的页面的DMA写入页错误。 I / O适配器尝试将DMA数据写入页面。确定页面无法写入。然后将DMA数据写入从替代页面池中选择的替代页面中的数据位置。然后将标志设置在每个数据位置的标志位置。标志位置对应于数据位置。当标志置位时，标志表示DMA数据存在于该标志位置对应的数据位置。

8. 发明授权

US07398427B2 Isolation of input/output adapter error domains 有权
标题翻译：输入/输出适配器错误域的隔离
公开(公告)号：US07398427B2
公开(公告)日：2008-07-08
申请号：US10887524
申请日：2004-07-08
申请人： Richard Louis Arndt , Patrick Allen Buckland , Gregory Michael Nordstrom , Steven Mark Thurber
发明人： Richard Louis Arndt , Patrick Allen Buckland , Gregory Michael Nordstrom , Steven Mark Thurber
IPC分类号： G06F11/00
CPC分类号： G06F11/2736
摘要： Method, apparatus and system for isolating input/output adapter error domains in a data processing system. Errors occurring in one input/output adapter are isolated from other input/output adapters of the data processing system by functionality in a host bridge that connects the input/output adapters to a system bus of the data processing system, thus permitting the use of low cost, industry standard switches and bridges external to the host bridge.
摘要翻译：用于在数据处理系统中隔离输入/输出适配器错误域的方法，装置和系统。在一个输入/输出适配器中发生的错误与数据处理系统的其他输入/输出适配器隔离，主机桥中的功能将输入/输出适配器连接到数据处理系统的系统总线，从而允许使用低成本，行业标准交换机和主桥外部的桥梁。

9. 发明申请

US20070297434A1 MECHANISM FOR DETECTING AND CLEARING I/O FABRIC LOCKUP CONDITIONS FOR ERROR RECOVERY 有权
标题翻译：用于检测和清除错误恢复的I / O织物锁定条件的机制
公开(公告)号：US20070297434A1
公开(公告)日：2007-12-27
申请号：US11426592
申请日：2006-06-27
申请人： Richard Louis Arndt , Thomas Schlipf , Steven Mark Thurber
发明人： Richard Louis Arndt , Thomas Schlipf , Steven Mark Thurber
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L41/0659 , H04L47/11 , H04L47/30 , H04L47/32 , H04L47/39 , H04L49/90
摘要： A computer implemented method, apparatus and mechanism for recovery of an I/O fabric that has become terminally congested or deadlocked due to a failure which causes buffers/queues to fill and thereby causes the root complexes to lose access to their I/O subsystems. Upon detection of a terminally congested or deadlocked transmit queue, access to such queue by other root complexes is suspended while each item in the queue is examined and processed accordingly. Store requests and DMA read reply packets in the queue are discarded, and load requests in the queue are processed by returning a special completion package. Access to the queue by the root complexes is then resumed.
摘要翻译：用于恢复I / O结构的计算机实现的方法，装置和机制，其由于导致缓冲器/队列填充并由此导致根配置失去对其I / O子系统的访问的故障而变得终端拥塞或死锁。在检测到最终拥塞或死锁传输队列时，暂停其他根组合对这样的队列的访问，同时对队列中的每个项目进行相应的检查和处理。队列中存储请求和DMA读回应数据包将被丢弃，队列中的加载请求将通过返回特殊的完成包进行处理。然后恢复根组合对队列的访问。

10. 发明授权

US06523140B1 Computer system error recovery and fault isolation 有权
标题翻译：计算机系统错误恢复和故障隔离
公开(公告)号：US06523140B1
公开(公告)日：2003-02-18
申请号：US09414337
申请日：1999-10-07
申请人： Richard Louis Arndt , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard Louis Arndt , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： H02H305
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0793
摘要： A method and implementing computer system is provided in which specific device identification information is acquired when a faulty condition is detected during an information transfer transaction, and the condition is reported to the device driver of the identified device for corrective action without initiating a system shut-down. In one example, PCI adapter sequence information, including tag number, requester bus number, requester device number and requester function number is captured and used in reporting an error condition in order to identify and isolate the adapter in a recovery operation.
摘要翻译：提供了一种方法和实现的计算机系统，其中在信息传输交易期间检测到故障状况时获取特定的设备识别信息，并且将该条件报告给所识别的设备的设备驱动程序以进行纠正，而不启动系统关闭，下。在一个示例中，捕获PCI适配器序列信息，包括标签号，请求者总线号，请求者设备号和请求者功能号，并用于报告错误状况，以便在恢复操作中识别和隔离适配器。

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